! RTISRS.RNO NAB/1738/SNLA 13-OCT-80/15-OCT-80. ! RT-11 INTERRUPT SERVICE ROUTINES. .PAPER SIZE 60,72 .DATE .NUMBER 0 .UPPER CASE .LEFT MARGIN 8 .RIGHT MARGIN 64 .TAB STOPS 8,16,24,32,40,48,56,64,72 .FIGURE 8 .CENTER RT-11 Interrupt Service Routines .CENTER By the Rules and Otherwise .CENTER or .CENTER Moral and Immoral .FIGURE 8 .CENTER N.#A.#Bourgeois, Jr. .CENTER Sandia National Laboratories .CENTER Systems Engineering Division 1738 .CENTER P.#O.#Box 5800 .CENTER Albuquerque ,NM 87185 .FIGURE 8 .CENTER Abstract .BLANK .PARAGRAPH RT-11's prescribed protocol for interrupt service routines is briefly described. More throughly described are several methods of writing interrupt service routines outside of the system rules. .FIGURE 8 .CENTER 80j15b .PAGE .LEFT MARGIN 16 .RIGHT MARGIN 56 .FIGURE 16 This document is issued by Sandia National Laboratories, operated for the United States Department of Energy by Sandia Corporation. .BLANK 2 .CENTER Notice .BLANK 2 This document was sponsored by the United States Government. Neither the United States Government nor the United States Department of Energy, nor any of their employees, nor any of their contractors, subcontractors, or their employees makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any information, apparatus, product or process disclosed, or represents that its use would not infringe privately owned rights. .BLANK 2 This work was sponsored and funded by: .BLANK .INDENT 4 Headquarters, ESD / OCB / Stop 36 .INDENT 4 Hanscom Air Force Base, MA 01731 .LEFT MARGIN 8 .RIGHT MARGIN 64 .PAGE .FIGURE 4 .CENTER Introduction .BLANK .PARAGRAPH Generally, the best way to respond to an external event is via an interrupt service routine (ISR). An interrupt is a forced transfer of program execution as a result of some external event. On interrupt the state of the processor is saved to permit a proper return once the interrupt has been serviced. The processor state for the ISR is obtained from two preassigned memory locations known as an interrupt vector. .PARAGRAPH While RT-11 [1] is faster than any of the other operating systems, its response time is longer than simple interrupt latency. RT-11's prescribed ISR protocol is responsible for this increased response time. As a result, it is possible for the system response time to interfere with a sufficiently fast data rate. Thus, it can become necessary to dispense with prescribed protocol (moral ISR) and use an immoral ISR. .PARAGRAPH First I will present a brief outline of moral ISR protocol. Then I'll describe several immoral ISR's. .BLANK 3 .CENTER Moral ISR's .BLANK .PARAGRAPH Chapter six of the Software Support Manual [2] offers an complete and excellent description of the prescribed ISR protocol. Hence, only an outline will be presented here. Some of the effects of the _.INTEN and the _.SYNCH macro calls are summarized in Table 1. The stack on entry into the ISR may be the system's or the user's depending on the state of the main program at the time of the interrupt. Figure 1.#shows an outline of a moral ISR along with an outline of its associated main program. This ISR protocol may be used in either the foreground (FG) or the background (BG) partition. .BLANK 2 .CENTER Effects#####New######Registers .CENTER Following###Stack####Available .BLANK .CENTER _.INTEN######System###R4,R5#### .CENTER _.SYNCH######User#####R0,R1#### .BLANK .CENTER Table 1. .PAGE .NOFILL .NOJUSTIFY MAIN: _.PROTECT ;grab the vector _.DEVICE ;set up a termination ;sequence ;Load the vector. ;Initialize buffers, flags and pointers. 1$: BISB _#100,@_#CSR ;enable the interrupt 2$: _.SPND ;wait for something to ;do ;Store and/or massage the data. ;If more to do ; reset flags, pointers and branch to 1$ or 2$ ;else ; go on to 3$ or 4$. 3$: ;Close files and clean up things. 4$: _.UNPROTECT ;release the vector _.EXIT ;end it all .BLANK ISR: ;Do what must be done at CPU priority 7. _.INTEN ;lower CPU priority ;Do more things here such as but not limited to ;bumping pointers and setting flags. ;If more data is required ; branch to 2$ ;else ; go on to 1$. 1$: _.SYNCH ;allow programmed ;requests _.RSUM ;wake up main program 2$: RTS PC ;monitor will issue RTI .BLANK .CENTER Figure 1. Moral ISR .FILL .JUSTIFY .BLANK 3 .CENTER Immoral ISR's .BLANK .PARAGRAPH Once the data rate becomes too high for RT-11 system response time it becomes necessary to use an immoral ISR. At this point some assumptions may be made. Only the one job exists. That job is run either under the single job (SJ) monitor, or is run in the BG partition under the foreground/background (FB) monitor with no FG job running. Under these conditions the ISR can be the same as for a memory only system. Figure 2.#shows an outline for such a situation. .PAGE .NOJUSTIFY .NOFILL MAIN: ;Load the vector. ;initialize buffers, flags and pointers. 1$: BISB _#100,@_#CSR ;enable the interrupt 2$: TST RDYFLG ;time to do something? BNE 2$ ;no ;Store and/or massage the data. ;If more to do ; reset flags, pointers and branch to 1$ or 2$ ;else ; go on to 3$ or 4$. 3$: ;Close files and cleanup things. 4$: _.EXIT ;end it all .BLANK ISR: ;Do what must be done immediatly. MOV SP,SPSAVE ;save the stack pointer MOV _#ISRSTK,SP ;set up a new stack CLR @_#PSW ;lower CPU priority ;(MTPS _#PR0 for LSI-11) ;Do more things here such as but not limited to ;bumping pointers and setting flags. MOV _#PR7,@_#PSW ;raise CPU priority ;(MTPS _#PR7 for LSI-11) MOV SPSAVE,SP ;restore original stack ;pointer RTI ;must issue own RTI .BLANK .CENTER Figure 2. SJ or BG Immoral ISR .FILL .JUSTIFY .BLANK .PARAGRAPH As with moral ISR's entry should be made at processor priority seven. No registers are available unless they are first saved and later restored. Also, note that all ISR code is not executed at processor priority seven. .PARAGRAPH It is also possible to run an immoral ISR in the FG partition if suitable care is exercised. Figure 3.#outlines the requirements for this situation. Once again no registers are available unless they are saved and restored. It is ablolutely essential to set up a new stack for this ISR in order to avoid problems with the system. When running an immoral ISR in the foreground partition the processor priority must be kept at seven. .PAGE .NOFILL .NOJUSTIFY MAIN: _.PROTECT ;grab the vector _.DEVICE ;set up termination ;sequence 1$: BISB _#100,@_#CSR ;enable the interrupt 2$: _.TWAIT ;go to sleep for a while ;Store and/or massage the data. ;If more to do ; reset flags, pointers and branch to 1$ or 2$ ;else ; go on to 3$ or 4$. 3$: ;Close files and cleanup things. 4$: _.UNPROTECT ;release the vector _.EXIT ;end it all .BLANK ISR: ;Do what must be done immediately. MOV SP,SPSAVE ;save original stack ;pointer MOV _#ISRSTK,SP ;set up new stack ;Do more things here such as but not limited to ;bumping pointers and setting flags. MOV SPSAVE,SP ;restore original stack ;pointer RTI ;must issue own RTI .BLANK .CENTER Figure 3. FG Immoral ISR .FILL .JUSTIFY .BLANK 3 .CENTER Concluding Remarks .BLANK .PARAGRAPH It has been shown that it is possible to write interrupt service routines both by the rules and outside the rules to operate under RT-11. No serious problems will be encountered if proper care is exercised with the use of the stack. If the ISR hogs enough processor time at priority seven it is possible to lose 60 Hz clock pulses. .FOOTNOTE 1 ! FILLS PAGE WITH BLANK LINES. ! END OF FOOTNOTE. .PAGE .FIGURE 4 .CENTER References .BLANK2 .LEFT MARGIN 12 .INDENT -4 1.##"RT-11, Version 4.0 Single-User Operating System", AE-3393M-TC, Digital Equipment Corporation, Maymard, MA, April 1980. .BLANK .INDENT -4 2.##"RT-11 Software Support Manual", AA-H379A-TC, Digital Equipment Corporation, Maynard, MA, March 1980. .FOOTNOTE 1 ! FILLS PAGE WITH BLANK LINES. ! END OF FOOTNOTE. .BREAK ! END OF FILE.