DMA2 DMA Core The DMA2 core is functionally equivalent to the LSI L64854 DMA controller and provides three channels for DMA over the SBus. It has three external interfaces designed to provide DMA access to one NCR92C990 Ethernet Controller (compatible with AMD7990), one NCR53C9X SCSI Controller (SCSI), and one programmable parallel port (Centronics-type). The DMA2 contains internal buffering for these DMA channels in the form of a cache for the ENET interface and FIFOs for the SCSI and parallel port interfaces. It also contains control/status registers for each of the three interfaces, several SCSI and parallel port support registers, and a write buffer for slave accesses to the ENET. the dewsign of the DMA2 is based on those of the SBUS DMA+ controller chip (LSI L645853A) and the parallel port from the SBus Hardcopy I/O Device (HIOD chip), and incorporates a number of new features for increasing performance and allowing different modes of operation necessary for new systems. By default, DMA2 is software compatible with DMA+. Software enables DMA2's additional features by changing the default values of appropriate mode bits in the control/status registers. Features - Supports 10 MByte/sec SCSI transfers, 1.25 MByte/sec Ethernet transfers, and 4 MByte/sec parallel port transfers. - Supports 4-word, 8-word, and 'no burst' SBus burst modes. - 64-byte internal cache for Etyhernet data buffering. - 64-byte internal FIFOs for SCSI and parallel port data buffering. - 16-bit write buffer for slave writes to ENET. - Improved cache and FIFO draining algorithms for better SBus utilization. - Internal address and byte count registers and "NEXT" address/byte count features for data block chaining on SCSI and parallel port interfaces. - JTAG test interface. DMA2 Enhanced Features - A configurable parallel port has been added and occupies one of the DMA channels. - A 16-bit buffer has been added for slave writes to the Ethernet controller. - The DMA2 forces the Ethernet to time-out on errors as well as generating an itnerrupt directly by asserting sb_e_irq_ when E_INT_EN is set. Prior to the DMA2, only the time-out would occur. - The E_ERR_PEND bit in the E_CSR is reset differently in the DMA2 mode of operation. (Refer to "E_CSR Bit Function Notes".) DMA2 Internal Registers ------------------------------------------------------------------------ | sb_a(x,y,z) | sb_a(4:0) | Register Accessed | Type | Size | ------------------------------------------------------------------------ | 000 | 00000 | Internal ID Register | R | 32 | ------------------------------------------------------------------------ | 010 | 00000 | SCSI Control/Status Register | R/W | 32 | ------------------------------------------------------------------------ | 010 | 00100 | SCSI Address Register | R/W | 32 | ------------------------------------------------------------------------ | 010 | 01000 | SCSI Byte Count Register | R/W | 32 | ------------------------------------------------------------------------ | 010 | 01100 | SCSI Test Control/Status Reg | R/W | 24 | ------------------------------------------------------------------------ | 010 | 10000 | Ethernet Control/Status Reg | R/W | 32 | ------------------------------------------------------------------------ | 010 | 10100 | Ethernet Test Control/Status | R/W | 32 | ------------------------------------------------------------------------ | 010 | 11000 | Ethernet Cache Valid Bits | R/W | 32 | ------------------------------------------------------------------------ | 010 | 11100 | Ethernet Base Address Reg | R/W | 32 | ------------------------------------------------------------------------ | 101 | 00000 | P-Port DMA Control/Status Reg| R/W | 8 | ------------------------------------------------------------------------ | 101 | 00100 | P-Port Address Register Reg | R/W | 32 | ------------------------------------------------------------------------ | 101 | 01000 | P-Port Byte Count Register | R/W | 32 | ------------------------------------------------------------------------ | 101 | 01100 | P-Port Test Control/Status | R/W | 32 | ------------------------------------------------------------------------ | 101 | 10000 | P-Port Hardware Config Reg | R/W | 32 | ------------------------------------------------------------------------ | 101 | 10010 | P-Port Operation Config Reg | R/W | 16 | ------------------------------------------------------------------------ | 101 | 10100 | P-Port Parallel Data Reg | R/W | 16 | ------------------------------------------------------------------------ | 101 | 10101 | P-Port Transfer Control Reg | R/W | 8 | ------------------------------------------------------------------------ | 101 | 10110 | P-Port Output Reg | R/W | 8 | ------------------------------------------------------------------------ | 101 | 10111 | P-Port Input Reg | R/W | 8 | ------------------------------------------------------------------------ | 101 | 11000 | P-Port Interrupt Control Reg | R/W | 16 | ------------------------------------------------------------------------ SCSI Registers (on 53C9X ASF) ------------------------------------------------------------------------ | sb_a(x,y,z) | sb_a(5:2) | Register Accessed | Type | Size | ------------------------------------------------------------------------ | 100 | 0000 | Transfer Count Low | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0001 | Transfer Count High | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0010 | FIFO Data | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0011 | Command | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0100 | Status/Bus ID | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0101 | Interrupt/Status Time-out | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0110 | Seq. Step/Sync transf period | R/W | 8 | ------------------------------------------------------------------------ | 100 | 0111 | FIFO flags/Synch offset | R/W | 8 | ------------------------------------------------------------------------ | 100 | 1000 | Configuration | R/W | 8 | ------------------------------------------------------------------------ | 100 | 1001 | Clock Conversion Factor | R/W | 8 | ------------------------------------------------------------------------ | 100 | 1010 | SCSI TEST (chip test only) | R/W | 8 | ------------------------------------------------------------------------ | 100 | 1011 | Configuration (SCSI-2 only) | R/W | 8 | ------------------------------------------------------------------------ ENET Registers (on NCR92C990 ASF) ---------------------------------------------------------------------- | sb_a(x,y,z) | sb_a(1) | Register Accessed | Type | Size | --------------------------------------------------------------------- | 110 | 0 | Register Data Port (RDP) | R/W | 16 | ---------------------------------------------------------------------- | 110 | 1 | Register Address Port (RAP) | R/W | 16 | ---------------------------------------------------------------------- SBus Interface The DMA2 provides for the communication between the SBus and three I/O devices, each of which are connected to seperate ports of the chip. One I/O device port is tailored to interface with the NCR92C990 Ethernet Controller, one port is tailored to interface with the NCR53C90X SCSI Controller, and one port implements a programmable Centronics-type parallel port. However, it is possible to interface with other I/O devices with some external logic. In this document, the three ports will be referred to as the ENET interface, the SCSI interface, and the parallel port interface, and it will be assumed that the ENET and SCSI are connected to their respective interfaces. Also, the three buffers associated with these interfaces will be referred to as the E-cache, the D-FIFO, and the P-FIFO, respectively. The DMA2 provides both Slave cycle and Master cycle accesses over the SBus. Address and Control registers in the DMA2 gate array, along with similar registers in both the ENET and the SCSI (or other devices in their places), can be accessed by the CPU via Slave cycles. Master Cycles To perform a Master Cycle the DMA2 requests the use of the SBus by asserting sb_br_, the bus request signal. On reception of sb_bg_, bus grant, the DMA2 takes control of the SBus to transfer data to or from memory, using the signals sb_d(31:0, sb_read, sb_siz(2:0), and sb_ack(2:0). The address is multiplexed onto the sb_d bus for all accesses on the SBus. The sizes of DMA reads from memory to the E-cache, D-FIFO, and P-FIFO are determined by the E_BURST_SIZE field in the E_CSR, the D_BURST_SIZE field in the D_CSR, and the P_BURST_SIZE field in the P_CSR, respectively. All reads to a given interface will be of the same size, either 1, 4 or 8 SBus words, depending on the value of the BURST_SIZE field in that interface's CSR. DMA writes from one of the interface buffers to memory can be any of the following sizes not greater than the corresponding read burst size: byte, half-word, word, 4-word, or 8-word. No 2-word bursts are carried out. The DMA2 SBus interface will always use the largest possible size when writing to memory. The largest possible size is determined by which bytes have been written to the DMA2 by the I/O device and the BURST_SIZE field in that device's CSR. Note that the slave device accessed by DMA2 must support the transfer sizes for which the chip is configured. The SBus interface of the DMA2 is capable of supporting rerun acknowledgments from slaves. The requested DMA transfer will repeat until either it completes or an error indicator (sb_ack(0) asserted) is received, it will unassert sb_br_ for one clock to give the CPU and other DMA masters a chance to win SBus arbitration. Then it will reassert sb_br_ to retry the cycle. Once the DMA2 has asserted sb_br_, it will not unassert it until it has received sb_bg_ or sb_reset_. Slave Cycles The CPU accesses registers in the DMA2 chip and attached devices by the use of a geographical select signal on the SBus, sb_sel_, in conjunction with sb_as_. During slave cycles the DMA2 takes control of the sb_ack(2:0) signals. The combination of responses are as follows: ------------------------------------------------------------------ | sb_ack(2) | sb_ack(1) | sb_ack(0) | Definition | ------------------------------------------------------------------ | 1 | 1 | 1 | Insert Wait States | ------------------------------------------------------------------ | 1 | 1 | 0 | Error ack | ------------------------------------------------------------------ | 1 | 0 | 1 | 8-bit Port ack | ------------------------------------------------------------------ | 1 | 0 | 0 | Rerun | ------------------------------------------------------------------ | 0 | 1 | 0 | Reserved | ------------------------------------------------------------------ | 0 | 0 | 1 | 16-bit Port ack | ------------------------------------------------------------------ | 0 | 1 | 1 | 32-bit Port ack | ------------------------------------------------------------------ | 0 | 0 | 0 | Reserved | ------------------------------------------------------------------ The DMA2 will give a rerun acknowledgment if a slave access is to an I/O device (SCSI or ENET) that is currently active with a DMA transfer, with one exception. The ENET interface is considered active with DMA if it is currently asserting the e_hlda_ or has asserted e_hlda_ within the one SBus clock. The SCSI interface is considered active with DMA if it is asserting d_ack_ or has asserted d_ack_ within two SBus clocks. The DMA2 contains a 16-bit write buffer for slave writes to ENET. This write buffer is enabled by default, but can be disabled by setting the E_DSBL_BUF_WR bit in the E_CSR. When E_DSBL_BUF_WR is not set, a single slave write to the ENET can be carried out without a rerun while it is active with a DMA transfer. A second slave write to the ENET while it is still active with a DMA transfer will elicit a rerun acknowledgment. The DMA2 will not give a rerun if a slave access is to an internal register of the DMA2; these accesses can take place concurrently with DMA activity between the I/O devices and the DMA2. Forcing the SBus master (usually the CPU) to rerun its slave accesses in this manner will insure that a deadlock does not occur between the SCSI or ENET and the SBus master. If the slave access to the DMA2 does not cause a rerun acknowledge, then the DMA2 will respond in the following way: ------------------------------------------------------------------ | Acknowledge | Field accessed | ------------------------------------------------------------------ | 32-bit port ack | Internal ID or internal register | ------------------------------------------------------------------ | 16-bit port ack | ENET register or 16-bit parallel port reg | ------------------------------------------------------------------ | 8-bit port ack | SCSI register, or external ID, or 8-bit | | | parallel port register | ------------------------------------------------------------------ | error ack | A byte or half-word access to an on-chip | | | register or a byte or word access to a ENET| | | register. Note that an error ack will also| | | be given for a register access of some size| | | other than a word, half-word, or byte. | ------------------------------------------------------------------ SBus Identification This is a mechanism which allows software to uniquely identify each SBus device, since each device can have a unique ID. The onboard ID of the DMA2 is hardwired to the 32-bit value 0xfe810103. This value will be returned when the ID firled is read by the CPU if the id_cs_ pin is tied low. If the id_cs_ pin is pulled high through a large (~4.7k) resistor, then access to the ID field will cause an external access using the id_cs_ pin as an external chip select. For offboard ID reads, ID data should be driven onto p_data(7:0) when id_cs_ is asserted. The sb_a bits can be used to address the external ID PROM. NOTE: For offboard ID reads (external to the DMA2), id_cs_ is simply an address decode from sb_a(x,y,z); therefore, it can be active for a slave read cycle or slave write cycle. The 89C100 provides an internal pullup on id_cs_, thus an external pull-up resistor is not required. Overview The DMA2 will provide all necessary buffering and arbitration functions to allow the ENET to access main memory over the SBus (master cycle) and the CPU to access the ENET (slave cycle). Between the ENET interface and the SBus interface is a 2 line, 8-word/line cache (E-cache) with consistency control logic. Each byte in the E-cache has its own valid/dirty bit, and each line has a bit that determines the meaning of the valid/dirty bits for that line (i.e. valid or dirty). These valid/dirty bits can be accessed directly for testing via the E_VLD register. Bytes being transferred to memory are marked dirty as they are loaded into the E-cache. Bytes being transferred from memory are marked as valid as they are loaded into the E-cache. Consistency control ensures that all data written by the ENET gets to main memory in a deterministic manner, and is handled completely in hardware. The ENET uses multiplexed address and data, so the DMA2 demultiplexes them internally. The address supported by the ENET is 24 bits. The upper 8 bits of the 32-bit virtual address for the ENET transfer come from the E_BASE_ADDR register, and by default are driven to 0xff. The ENET has a 16-bit data path which can accommodate 8 or 16 bit accesses using byte masking capabilities. Data packing and unpacking is used to reduce bus bandwidth impact of ENET transfers on the SBus. The ENET performs 2 distinct types of memory access; data transfer from or to the network, and message descriptor access for buffer management control. The ENET performs data transfers in bursts of up to 8 half-word accesses (16 bytes total), and message descriptor transfers as single half-word accesses. The end of a ENET transfer is detected by the unassertion of the e_hold_ signal. NOTE: Any I/O device connected to the ENET interface of the DMA2 is required to unassert e_hold_ between write cycles and read cycles, and it is not allowed to unassert e_hold_ during the e_as_ or e_das_ pulses, or between these pulses. Transfers To Memory Data from the ENET is packed into the E-cache and marked as "dirty" until one of the draining conditions is detected. The nine conditions that can cause draining of dirty bytes to memory are as follows: 1) The ENET writes to the last byte of a E-cache line. 2) The ENET writes a message descriptor (disabled by setting E_DSBL_WR_DRN bit in E_CSR). 3) The CPU does a slave read of a ENET CSR (disables by setting E_DSBL_RD_DRN bit in E_CSR). 4) The CPU does a slave write to a ENET CSR (disabled by setting E_DSBL_WR_INVAL bit in E_CSR). 5) The E_DRAIN bit in the E_CSR is set. 6) The E_INVALIDATE bit in the E_CSR is set. 7) The E_RESET bit in the E_CSR is set. 8) Both E-cache lines contain dirty data when the ENET writes to an address that causes a cache miss. 9) The ENET performs a DMA read from the E-cache after having performed a DMA write to the E-cache. None of these conditions will cause darining if E_ERR_PEND=1, indicating that a memory error has occurred. If Condition 4, 6, or 7 occurs when the E_ERR_PEND=1, the E-cache will be invalidated and all dirty data discarded. Condition 1 will always cause the dirty bytes in that cache line to be queued for draining to memory, while data can continue to be written into the other line if the ENET is still transferring. The last byte of a cache line is the byte whose least significant address bits are 0xf or 0x1f, depending on the E_BURST_SIZE field in the E_CSR. COndition 2, the ENET writing a descriptor, indicates that it has completed transferring a data block or has detected an error in transferring, and is detected as a single half-word written during a single assertion of e_hold_. This draining condition can be disabled by setting the E_DSBL_WR_DRN bit in the E_CSR. Condition 5 provides a way for the CPU to explicitly drain all dirty bytes in the cache by setting the E_DRAIN bit in the E_CSR. The E_DRAIN bit clears itself once draining is complete. COndition 8 occurs when the ENET attempts to write data to an address that doesn't match one of the cache tage and bot cache lines contain dirty data. In this case, both cache lines will automatically be queued for draining in order to make room for the new data to be written. Condition 9 ensures that the ENET doesn't write data to the E-cache and then read it back before the E-cache has a chance to drain the data to memory. Note that if an I/O device connected to the ENET interface makes more than one write to the same address without satisfying one of the draining conditions, the data previously stored at that address in the E-cache will be written over each time new data is written to that address. Transfers From Memory If the data requested by the ENET is not in the E-cache or marked as not valid, then the Least Recently Used (LRU) E-cache line will be filled with the line from memory that contains the data requested. As soon as the data requested by the ENET is written to the E-cache, it is transferred on the ENET (even if the entire E-cache line has not yet been filled). Also, the word containing the requested data will be the first one to be read from memory. If the data requested by the ENET is in the E-cache and it si valid, then the ENET gets a cache hit, and the requested data is transferred to the ENET and marked as no longer valid in the E-cache. If part of all of the data requested by the ENET comes from a byte in an E-cache line whose least significant address bits are 0x6, and the next cache line is on the same 4k page as the current line, then a read-ahead operation will be performed. When a read-ahead occurs, the E-cache line that does not contain the data requested by the ENET will be filled with the next line from memory. The read-ahead happens concurrently with the transfer of the requested data to the ENET unless the ENET's request resulted in a cache miss. If the ENET receives a cache miss on a request that causes a read-ahead, then the e_rdy_ signal will not be asserted to the ENET until the SBus burst transfer (caused by the cache miss) has completed. Positioning the read-ahead line as it is, at byte 6 of the cache line, causes data from large blocks to be automatically pre-fetched, but does not cause superfluous pre-fetches on descriptor reads. When the last byte of a cache line is accessed, the other line is marked as Most Recently Used (MRU). Otherwise, the line that was most recently accessed by the ENET is marked as MRU. The line that is not marked as MRU is marked as LRU. There are several conditions that will cause all valid data that has been read into the E-cache from memory to be invalidated before it can be read by the ENET. If the ENET reads the same address more than once without any intervening DMA access to the DMA2, then the DMA2 detects that the ENET is polling and marks all bytes in the E-cache as invalid. This ensures consistency between the E-cache and memory for the data that is in the same cache line as the accessed data. A CPU slave write to any of the ENET's internal registers will also cause all bytes in the E-cache to be marked invalid if the E_DSBL_WR_INVAL bit in the E_CSR is 0. If E_DSBL_WR_INVAL=1, the E-cache is unaffected by slave writes to the ENET, which has been shown to markedly increase the performance of the ENET driver software. These and the other conditions that invalidate all bytes in the E-cache are summarized as followed: 1) The ENET reads the same address more than once without intervening DMA accesses (polling). 2) The CPU does a slave write to a ENET internal CSR (disabled by setting E_DSBL_WR_INVAL in E_CSR). 3) The E_INVALIDATE bit in the E_CSR is set. 4) The E_RESET bit in the E_CSR is set. 5) sbus_reset_ is asserted. Memory Errors A transfer from the ENET to memory is composed of two separate transfers: one from the ENET to the DMA2, and another from the DMA2 to memory. Similarly, a transfer from memory to the ENET is composed of a transfer from memory to the DMA2, and another from the DMA2 to the ENET. A memory error can only occur during a transfer between the DMA2 and memory. The DMA2 reports ENET-related memory errors by setting the E_ERR_PEND bit in the E_CSR. When E_ERR_PEND is set, the DMA2 forces the ENET to time out by witholding e_rdy after it has asserted e_hlda. It then generates an interrupt request directly to the CPU by asserting sb_e_irq_ when interrupts are enabled by E_INT_EN being set. This gives rise to two interrupt sources, ENET and DMA2, both of which must be cleared by software. This can be done in one of two ways, either by setting the E_RESET bit in the E_CSR, which resets the ENET and clears E_ERR_PEND, or by resetting the ENET by writing to its internal control register and then clearing E_ERR_PEND by writing E_INVALIDATE. E_ERR_PEND is not cleared by a slave write to the ENET. To restart ENET DMA activity after an error, it will be necessary to write to the ENET's internal registers. If the E_DSBL_WR_INVAL bit in the E_CSR is set, software must invalidate the E-cache explicity so that invalid cache data is not used when the ENET is restarted. For a memory time-out or protection error on a transfer from the ENET to memory, the DMA2 behaves in the following way: The E_ERR_PEND bit in the E_CSR is set as soon as the error is detected. This causes the DMA2 to generate an interrupt (assert sb_e_irq_) if interrupts are enabled by E_INT_EN being set. No further transfers from the DMA2 to memory will take place until the E_ERR_PEND bit is cleared. For a memory time-out or protection error on a transfer from memory to the ENET, the DMA2 behaves in the following way: The E_ERR_PEND bit in the E_CSR is set as soon as the error is detected. This causes the DMA2 to generate an interrupt (assert sb_e_irq_) if interrupts are enabled by E_INT_EN being set. No further transfers to the ENET takes place until the E_ERR_PEND bit is cleared. Registers Internal to the ENET Slave accesses to the ENET registers will be completed with a 16-bit port acknowledge signal, sb_ack(2) & sb_ack(1), as defined in the SBus specification. The CPU accesses registers internal to the ENET in the same way as it does registers internal to DMA2, by asserting DMA2's sb_sel_ in conjunction with sb_as_. The address map for these registers is shown in Table 3-3. Registers Internal to DMA2 Ethernet Control/Status Register (E_CSR) ---------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------------- | 31:0| E_CSR | Control/Status bits for Ethernet Interface | R/W | ---------------------------------------------------------------------------- The E_CSR is a 32-bit R/W register internal to DMA2 and is accessed as indicated in the DMA2 Internal Registers Address Map (Table 3-1). The bits in the E_CSR are defined in the following table: E_CSR Bit Definitions ---------------------------------------------------------------------------- | Bit | Memonic | Description | Type | ---------------------------------------------------------------------------- | 0 | E_INT_PEND | Set when e_irq_ active, cleared when| R | | | | e_irq_ inactive. | | ---------------------------------------------------------------------------- | 1 | E_ERR_PEND | Set when memory time-out, protection| R | | | | or late error detected on a ENET | | | | | transfer. | | ---------------------------------------------------------------------------- | 3:2 | E_DRAINING | Both bits set when E-cache draining | R | | | | dirty data to memory, otherwise | | | | | both bits are 0. | | ---------------------------------------------------------------------------- | 4 | E_INT_EN | When set, enables sb_e_irq_ to | R/W | | | | assert when E_INT_PEND or E_ERR_PEND| | | | | is set. | | ---------------------------------------------------------------------------- | 5 | E_INVALIDATE | When set, marks all bytes in E-cache| W | | | | as invalid. Resets itself. Reads as| | | | | zero. | | ---------------------------------------------------------------------------- | NOTE: All bits in the E_CSR default to 0 on an E_RESET or Sbus reset | | with the following exceptions: E_RESET itself is cleared by an | | SBus reset but otherwise remains active once set until written | | zero and E_DEV_ID is hard-wired to 1010. | ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- | Bit | Memonic | Description | Type | ---------------------------------------------------------------------------- | 6 | E_SLAVE_ERR | Set on slave access size error to a | R/W | | | | ENET-related register. Reset on | | | | | write of 1. | | ---------------------------------------------------------------------------- | 7 | E_RESET | When set, invalidates the E-cache, | R/W | | | | resets the ENET interface, and | | | | | asserts e_reset. | | ---------------------------------------------------------------------------- | 9:8 | -- | Unused. Read as 0. | R | ---------------------------------------------------------------------------- | 10 | E_DRAIN | When set, forces draining of E-cache| R/W | | | | Resets itself when draining complete| | ---------------------------------------------------------------------------- | 11 | E_DSBL_WR_DRN | When set, disables draining of | R/W | | | | E-cache on descriptor writes from | | | | | ENET. | | ---------------------------------------------------------------------------- | 12 | E_DSBL_RD_DRN | When set, disables draining of | R/W | | | | E-cache on slave reads to ENET. | | ---------------------------------------------------------------------------- | 14:13 | -- | Unused. Read as 0. | R | ---------------------------------------------------------------------------- | 15 | E_ILACC | When set, modifies ENET DMA cycle. | R/W | ---------------------------------------------------------------------------- | 16 | E_DSBL_BUF_WR | When set, disables buffering of | R/W | | | | slave writes to ENET. | | ---------------------------------------------------------------------------- | 17 | E_DSBL_WR_INVAL | Defines whether E-cache is | R/W | | | | invalidated on slave writes to ENET | | | | | 1 = no invalidate | | ---------------------------------------------------------------------------- | 19:18 | E_BURST_SIZE | Defines size of SBus read and write | R/W | | | | bursts for ENET transfers (see table| | | | | below). | | ---------------------------------------------------------------------------- | 20 | -- | Unused. | R/W | ---------------------------------------------------------------------------- | 21 | E_LOOP_TEST | When set, enables Ethernet loop- | R/W | | | | back mode by tristating TP_AUI_ | | | | | output. | | ---------------------------------------------------------------------------- | 22 | E_TP_AUI_ | When E_LOOP_TEST = 0, selects TP or | R/W | | | | AUI Ethernet by driving TP_AUI to 1 | | | | | or 0. | | ---------------------------------------------------------------------------- | 27:23 | -- | Unused. Read as 0. | R | ---------------------------------------------------------------------------- | 31:28 | E_DEV_ID | Device ID (For DMA2, E_DEV_ID=1010) | R | ---------------------------------------------------------------------------- | NOTE: All bits in teh E_CSR default to 0 on an E_RESET or SBus reset with| | the following exceptions: E_RESET itself is cleared by an SBus | | reset but otherwise remains active once set until written to 0 and | | E_DEV_ID is hard-wired to 1010. | ---------------------------------------------------------------------------- E_CSR Bit Function Notes E_ERR_PEND - Bit 1 E_ERR_PEND is always reset on setting E_INVALIDATE or E_RESET. E_DRAINING - Bits 3:2 When the E-cache is draining to memory, both bits are set. Do NOT assert E_RESET or E_INVALIDATE when set. E_DRAINING bits are not valid while E_ERR_PEND is set or during transfers to the ENET. In these cases, the E_DRAINING bits should be ignored. E_INT_EN - Bit 4 Setting this bit allows the DMA2 to generate an interrupt by asserting sb_e_irq_ whenever E_INT_PEND is set due to the ENET asserting e-Irq_, or whenever E_ERR_PEND is set due to a memory error. E_INVALIDATE - Bit 5 Setting this bit invalidates the E-cache. If E_ERR_PEND=0 when E_INVALIDATE is set, all dirty data in the E-cache will first be drained to memory. If E_ERR_PEND=1 when E_INVALIDATE is set, all dirty data in the E-cache will be discarded. In addition to invalidating the E-cache, setting this bit causes E_ERR_PEND to be reset. E_RESET - Bit 7 E_RESET will remain active once written as a one until written as a zero, unless cleared by an SBus reset (sb_reset_ asserted). Setting E_RESET or asserting sb_reset_ will invalidate the E-cache, reset all ENET interface state machines to their idle states, and assert the e_reset output for as long as E_RESET or sb_reset_ remains active. If E_ERR_PEND=0 when E_RESET is set, all dirty bytes in the E-cache will first be drained to memory. When this occurs, E_RESET must not be cleared until draining is complete, as indicated by E_DRAINING=00. If E_ERR_PEND=1 when E_RESET is set, no draining will take place and all dirty data in the E-cache will be discarded. If the CPU attempts a slave access to the ENET while E_RESET or sb_reset_ is active, it will not cause an error, but no data will actually be transferred since the e_reset output is being asserted throughout the access. In order to satisfy the ENET chip's minimum reset pulse width (200 ns), E_RESET must remain set for at least 10 SBus clocks. E_DSBL_WR_DRN - Bit 11 When E_DSBL_WR_DRN=0, dirty bytes in the E-cache are queued for draining to memory whenever the ENET writes to a message descriptor. This is detected as a ENET transfer (one assertion of e_hold_) in which only a single half_word is written. When E_DSBL_WR_DRN=1, draining of the E-cache on this condition is disabled. E_DSBL_RD_DRN - Bit 12 When E_DSBL_RD_DRN=0, dirty bytes in the E-cache are queued for draining to memory whenever the CPU does a slave read to one of the ENET CSR's. When E_DSBL_RD_DRN=1, draining of the E-cache on this condition is disabled. E_ILACC - Integrated Local Area Controller Chip - Bit 15 When ENET (or something in its place) is master, and it performs a DMA cycle with ILACC set, e_rdy_ will go inactive when the ENET unasserts d_das_ and e_hlda_ will go inactive when e_hold_ is unasserted. Note that neither e_das_ nor e_hold_ can glitch when the ILACC bit is set. E_DSBL_WR_BUF - Bit 16 Setting this bit disables the 16-bit buffer for slave writes to ENET. E_DSBL_WR_INVAL - Bit 17 When E_DSBL_WR_INVAL=0, the E-cache is invalidated whenever the CPU does a slave write to the ENET. When E_DSBL_WR_INVAL=1, the E-cache is not invalidated on slave writes to ENET. The latter mode significantly increases tolerable SBus latency while the ENET is transmitting Ethernet data. E_BURST_SIZE - Bits 19:18 This field defines the sizes of SBus read and write bursts used by DMA2 for ENET transfers and the size of the E-cache lines. All reads from memory will be one size, either 4- or 8-word SBus burst. SBus writes to memory can be byte, halfword, or word, or one of the burst sizes given in the table. The DMA2 will always use the largest possible size for writes, which is dependent on E_BURST_SIZE and the number of dirty bytes that need to be drained. Also, E_BURST_SIZE determines the size of the E-cache lines, which are the same size as the SBus read burst. The sizes given in the following table are in SBus words: -------------------------------------------------------------------------- | E_BURST_SIZE | Read Burst Size | Write Burst Sizes | E-cache Line Size | -------------------------------------------------------------------------- | 00 | 4 words | 4 words | 4 words | -------------------------------------------------------------------------- | 01 | 8 words | 4, 8 words | 8 words | -------------------------------------------------------------------------- | 01 | reserved | reserved | reserved | -------------------------------------------------------------------------- | 01 | reserved | reserved | reserved | -------------------------------------------------------------------------- E_LOOP_TEST & E_TP_AUI_ - Bits 21 & 22 These bits determine the value of the TP_AUI_ output pin, which drives the NIS input pin of the external T7213 dual Ethernet interface chip. TP_AUI_ selects between the T7213's TP, AUI, and loopback Ethernet modes by driving its NIS input as indicated in the following table: -------------------------------------------------------------------- | E_LOOP_TEST | E_TP_AUI_ | TP_AUI_ | TP_AUI_Function | -------------------------------------------------------------------- | 0 | 0 | 0 | NIS Select-AUI mode | -------------------------------------------------------------------- | 0 | 1 | 1 | NIS Select-TP mode | -------------------------------------------------------------------- | 1 | X | Z | NIS Select-Loopback mode | -------------------------------------------------------------------- | NOTE: At least 20mS must elapse after any change to the TP_AUI_ | | output before transferring data to or from the T7213. | -------------------------------------------------------------------- Ethernet Address Register (E_ADDR) -------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | -------------------------------------------------------------------- | 23:0 | E_ADDR | Ethernet DMA Address Register | R/W | -------------------------------------------------------------------- This register holds bits (23:0) of the address at which the ENET is requesting a DMA transfer. Bits (31:24) of the ENET DMA address are driven by the E_BASE_ADDR register, and have a default value of 0xff. During normal operation, the E_ADDR register is never read or written directly from the SBus, but for testing purposes it can be accessed via bits (23:0) of the E_TST_CSR as described in the following section. Ethernet Test Control/Status Register (E_TST_CSR) The E_TST_CSR is a 32-bit R/W register internal to DMA2 provided for testability purposes. It is accessed as indicated in the DMA2 Internal Registers Address Map (Table 3-1). The read and write functions of the bits in the E_TST_CSR are defined in the following table: ----------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ----------------------------------------------------------------------- | 31 | LD_TAG | Writing 1 loads address tag or LRU | W | | | | cache line with E_TST_CSR(23:0) | | ----------------------------------------------------------------------- | 30 | REQ_OUT | Reads as 1 when cache is making a | R | | | | request for an SBus read or write. | | ----------------------------------------------------------------------- | 30 | RD_LINE | Writing a 1 initiates a burst read | W | | | | from memory into LRU cache line | | | | | from address in E_ADDR. | | ----------------------------------------------------------------------- | 29 | HIT | Reads as 1 when address in E_ADDR | R | | | | matches one of the cache address | | | | | tags and corresponding valid bit | | | | | is set. Not valid while E_HLDA_ | | | | | asserted. (ENET DMA active). | | ----------------------------------------------------------------------- | 28 | LRU | Reads as which cache line is LRU | R/W | | | | (1 or 0). Writing marks specificed | | | | | cache line as LRU. | | ----------------------------------------------------------------------- | 27 | DRAIN1 | Reads as 1 if cache line 1 is | R/W | | | | draining. Writing to 1 causes dirty| | | | | bytes in cache line 1 to drain. | | ----------------------------------------------------------------------- | 26 | DRAIN0 | Reads as 1 if cache line 0 is | R/W | | | | draining. Writing to 1 causes dirty| | | | | bytes in cache line 0 to drain. | | ----------------------------------------------------------------------- | 25 | DIRTY1 | Determines meaning of Valid/Dirty | R/W | | | | bits for cache line 1. | | ----------------------------------------------------------------------- | 24 | DIRTY0 | Determines meaning of Valid/Dirty | R/W | | | | bits for cache line 0. | | ----------------------------------------------------------------------- | 23:0 | E_ADDR | Reads E_ADDR register. | R | ----------------------------------------------------------------------- | 23:0 | E_ADDR | Writed E_ADDR register. If | W | | | | LD_TAG=1, also writed LRU cache | | | | | address tag. | | ----------------------------------------------------------------------- Note: The E_TST_CSR is intended for diagnostic and test use only, and should never be written while a DMA transfer is active. Ethernet Cache Valid Bits Register (E_VLD) ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 31:0 | E_VLD | Valid/Dirty bits for LRU Ethernet | R/W | | | | Cache Line | | ---------------------------------------------------------------------- Note: The E_VLD register is intended for diagnostic and test use only, and should never be written while a DMA transfer is active. This register accesses the bits which indicate whether each byte in the Least Recently Used cache line is valid, invalid, dirty, or not dirty. Each bit corresponds to the byte of the same number in the LRU cache line. The meaning of these bits for each cache line is determined by the DIRTY1 and DIRTY0 bits, accessible through the E_TST_CSR. The following table describes the meaning of the E_VLD bits based on the value of DIRTY1/0 bit corresponding to the LRU cache line: ---------------------------------------------------------------------- | DIRTY 1/0 | E_VLD Bit | Meaning | ---------------------------------------------------------------------- | 0 | 0 | Invalid data; reading this byte is a cache | | | | miss. | ---------------------------------------------------------------------- | 0 | 1 | Valid data; reading this byte is a cache | | | | hit. | ---------------------------------------------------------------------- | 1 | 0 | Not dirty data; thisbyte does not need to | | | | be drained to memory. | ---------------------------------------------------------------------- | 1 | 1 | Dirty data; this byte needs to be drained | | | | to memory. | ---------------------------------------------------------------------- Ethernet Base Address Register (E_BASE_ADDR) ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 7:0 | E_BASE_ADDR| High Order 8 bits of address for | R/W | | | | Ethernet DMA transfers (defaults to | | | | | 0xff). | | ---------------------------------------------------------------------- This register makes the high order 8 address bits which are driven onto the SBus for Ethernet DMA transfers programmable by software. By default, these bits are always driven to 0xff, but for some applications it is useful to set a base address. SCSI Interface Overview The DMA2 gate array provides paths for the SCSI to transfer data to and from memory and for the CPU to access control and status registers on the SCSI. In order to support the DMA activity of the SCSI, the DMA2 contains two 24-bit address counters, a 32-bit control/status register as well as two 24 bit byte counters which may be used for a SCSI generic control of future devices. The SCSI has a 16-bit transfer count, however the address counter supports 24-bit count for future enhancements. Between the SCSI interface and the SBus interface is a 64-byte FIFO (D-FIFO). This FIFO is bypassed for slave accesses to the SCSI. For error recovery, the D_CSR contains a D_INVALIDATE bit for explicity invalidating the FIFO. Transfers To Memory Data from the SCSI is written into the D-FIFO until the largest possible SBus burst write to memory can be carried out (1, 4, or 8 words depending on the D_BURST_SIZE field in the D_CSR). All data in the D-FIFO is then queued for draining to memory. Any time a SCSI interrupt, byte count expiration, slave write to the D_CSR, or slave access to a SCSI-internal register is detected, data in the D-FIFO is also queued for draining. The last two conditions can be disabled by setting appropriate mode bits in the D_CSR. When the D-FIFO is invalidated by setting the D_INVALIDATE or D_RESET bits in the D_CSR, all data currently in the D-FIFO will first be drained to memory unless the D_ERR_PEND bit is set. If D_ERR_PEND is set when D_INVALIDATE or D_RESET is asserted, or an SBus reset occurs (sb_reset_ is asserted), any data in the D-FIFO will be discarded. These and other conditions that cause data in the D-FIFO to be drained to memory are summarized below: 1) 4, 16, or 32 bytes (depending on D_BURST_SIZE) have been written to the D-FIFO by the SCSI. 2) The D_INT_PEND bit in the D_CSR is set. 3) The CPU does a slave write to the D_CSR (disabled by setting D_DSBL_CSR_DRN bit in D_CSR). 4) The CPU does a slave access to a SCSI-internal register (disabled by setting D_DSBL_SCSI_DRN bit in D_CSR). 5) The D_RESET or D_INVALIDATE bit in the D_CSR is set. 6) The D_ADDR register is loaded with a new address, either directly or from the D_NEXT_ADDR register (disabled by setting D_DIAG bit in D_CSR). None of these conditions will cause draining if D_ERR_PEND=1, indicating that a memory error has occurred. If Condition 5 or 6 occurs when D_ERR_PEND=1, that D-FIFO will be invalidated and all dirty data discarded. Draining is carried out completely in hardware and until it is completed, subsequent DMA reads from the SCSI are inhibited (by witholding d_ack_). A mechanism for determining when the D-FIFO has been drained is provided in the D_CSR. Transfers From Memory When the SCSI initiates a read operation, the DMA2 does an SBus read burst of the size defined by D_BURST_SIZE, either 1, 4, or 8 SBus words. The word containing the requested data will be the first one to be read from memory and will be transferred on to the SCSI as soon as it is written to the D-FIFO, even before the rest of the burst read is complete. When the SCSI is reading data and the D-FIFO has enough space to hold another read burst of data (4, 16, or 32 bytes, depending on D_BURST_SIZE), a read-ahead operation will be performed as long as it doesn't cross a 4K page boundary. When this occurs, the largest possible SBus burst read is performed beginning with the address of the word following the last word in the D-FIFO. The read-ahead happens concurrently with the transfer of data to the SCSI. Memory Errors A transfer from the SCSI to memory is composed of two separate transfers: one from the SCSI to the DMA2, and another from the DMA2 to memory. Similarly, a transfer from memory to the SCSI is composed of a transfer from memory to the DMA2, and another from the DMA2 to the SCSI. A memory error can only occur in a transfer between the DMA2 and memory. The DMA2 reports SCSI-related memory errors by setting the D_ERR_PEND bit in the D_CSR, which generates an interrupt request (asserts sb_d_irq_) to the CPU when enabled by D_INT_EN being set. When D_INT_EN is set, sb_d_irq will also be asserted (level sensitive) whenever d_irq_ is asserted by the SCSI. For a memory time-out or protection error on a transfer from the SCSI to memory, the DMA2 behaves in the following way: The D_ERR_PEND bit in the D_CSR is set as soon as the error is detected, causing the DMA2 to generate an interrupt (assert sb_d_irq_) if interrupts are enabled by D_INT_EN being set. After the transfer that caused the error, no further transfers will take place from the DMA2 to memory. The interrupt is active until the D_ERR_PEND bit has been cleared by setting the D_INVALIDATE or D_RESET bits. For a memory time-out or protection error on a transfer from memory to the SCSI, the DMA2 behaves in the following way: Since the DMA2 reads data that the SCSI has not yet requested (without crossing page boundaries), it is possible that an error could be detected on a data read that the SCSI has never requested. Whether the SCSI requested the memory read that caused the error or not, the data from that read will not be written to the SCSI. Instead the D_ERR_PEND bit is set, which causes the DMA2 to generate an interrupt (assert sb_d_irq_) if interrupts are enabled by D_INT_EN being set. No transfers to the SCSI take place until D_ERR_PEND is cleared. Registers Internal to the SCSI Access to control and status registers in the SCSI are achieved using the address map in Table 3-2. These addresses are external to the DMA2, however the chip does decode the appropriate higher order address bits, sb_a(x, y, z) = 100, and generate the chip select and read/write lines to the external device. The DMA2 responds to slave accesses of these registers with sb_ack(1). SCSI Support Registers Internal to DMA2 Access to SCSI support registers within DMA2 are achieved using the address map in Table 3-1. These registers provide status and control for the SCSI and are selected by the host when sb_sel_ and sb_as_ are zero and sb_a(x, y, z) = 010. The Next feature registers are selected when D_EN_NEXT=1. The Byte Count Registers are only used when enabled by bit 13, D_EN_CNT, in the D_CSR. SCSI Control/Status Register (D_CSR) -------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | -------------------------------------------------------------------------- | 31:0 | D_CSR | Control/Status bits for SCSI Interface | R/W | -------------------------------------------------------------------------- The D_CSR is a 32-bit R/W register internal to DMA2 and is accessed as indicated in the DMA2 Internal Registers Address Map (Table 3-1). The bits in the D_CSR are defined in the following table: D_CSR Bit Definitions ---------------------------------------------------------------------------- | Bit | Memonic | Description | Type | ---------------------------------------------------------------------------- | 0 | D_INT_PEND | Set when d_irq active, or when D_TC | R | | | | set and D_TCI_DIS not set. Cleared | | | | | otherwise. | | ---------------------------------------------------------------------------- | 1 | D_ERR_PEND | Set when memory time-out, protection| R | | | | or late error detected on SCSI DMA | | | | | transfer. | | ---------------------------------------------------------------------------- | 3:2 | D_DRAINING | Both bits set when D-FIFO draining | R | | | | SCSI data to memory, otherwise | | | | | both bits are 0. | | ---------------------------------------------------------------------------- | 4 | D_INT_EN | When set, enables sb_d_irq_ to | R/W | | | | assert when D_INT_PEND or D_ERR_PEND| | | | | is set. | | ---------------------------------------------------------------------------- | 5 | D_INVALIDATE | When set, invalidates the D-FIFO. | W | | | | Resets itself. Reads as zero. | | ---------------------------------------------------------------------------- | 6 | D_SLAVE_ERR | Set on slave access size error to a | R/W | | | | SCSI-related register. Reset on | | | | | write of 1. | | ---------------------------------------------------------------------------- | 7 | D_RESET | When set, invalidates the D-FIFO, | R/W | | | | resets the SCSI interface, and | | | | | asserts d_reset output. | | ---------------------------------------------------------------------------- | 9 | D_EN_DMA | When set, enables DMA requests from | R/W | | | | SCSI if DMA not stopped by other | | | | | conditions. | | ---------------------------------------------------------------------------- | 12:10 | -- | Unused. Read as 0. | R | ---------------------------------------------------------------------------- | 13 | D_EN_CNT | When set, enables internal byte | R/W | | | | counter, D_BCNT, to be decremented | | | | | on byte transfers. | | ---------------------------------------------------------------------------- | 14 | D_TC | Terminal Count; set when D_BCNT has | R/W | | | | expired. Reset on write of 1 if | | | | | D_EN_NEXT=1. | | ---------------------------------------------------------------------------- | 15 | -- | Unused. Read as 0. | R | ---------------------------------------------------------------------------- | 16 | D_DSBL_CSR_DRN | When set, disables draining of | R/W | | | | D-FIFO on slave writed to D_CSR. | | ---------------------------------------------------------------------------- | 17 | D_DSBL_SCSI_DRN | When set, disabled draining of | R/W | | | | D-FIFO on slave accesses to | | | | | SCSI-internal registers. | | ---------------------------------------------------------------------------- | 19:18 | D_BURST_SIZE | Defines size of SBus read and write | R/W | | | | bursts for SCSI transfers (see table| | | | | below). | | ---------------------------------------------------------------------------- | 20 | D_DIAG | When set, disables draining and | R/W | | | | resetting of D-FIFO on writing of | | | | | D_ADDR register. | | ---------------------------------------------------------------------------- | 21 | D_TWO_CYCLE | When set, and D_FASTER=0, sets SCSI | R/W | | | | DMA transfer rate to (2 SBus clocks)| | | | | /byte. | | ---------------------------------------------------------------------------- | 22 | D_FASTER | When set and D_TWO_CYCLE=0, sets | R/W | | | | SCSI DMA transfer rate to (3 SBus | | | | | clocks)/byte. | | ---------------------------------------------------------------------------- | 23 | D_TCI_DIS | When set, disabled D_TC from | R/W | | | | generating an interrupt. Defaults | | | | | to 0. | | ---------------------------------------------------------------------------- | 24 | D_EN_NEXT | When set, enables next address auto-| R/W | | | | load mechanism. D_EN_CNT must also | | | | | be set. | | ---------------------------------------------------------------------------- | 25 | D_DMA_ON | When set, indicates that the DMA2 is| R | | | | able to respond to DMA requests from| | | | | the SCSI. | | ---------------------------------------------------------------------------- | 26 | D_A_LOADED | Address Loaded. Set when D_ADDR | R | | | | written or NEXT_ADDR copied to | | | | | DADDR. | | ---------------------------------------------------------------------------- | 27 | D_NA_LOADED | Next Address Loaded. Set when | R | | | | NEXT_ADDR register written. | | ---------------------------------------------------------------------------- | 31:28 | D_DEV_ID | Device ID (For DMA2, D_DEV_ID=1010) | R | ---------------------------------------------------------------------------- Note: All bits in the D_CSR default to 0 on a D_RESET or SBus reset with the following exceptions: D_RESET itself is cleared by an SBus reset but otherwise remains active once set until written to 0 and D_DEV_ID is hard-wired to 1010. D_CSR Bit Function Notes D_ERR_PEND - Bit 1 DMA to/from the SCSI is stopped while this bit is set. D_ERR_PEND is reset on setting D_INVALIDATE or D_RESET. D_DRAINING - Bits 3:2 When D-FIFO is draining to memory, both bits are set. Do not assert D_RESET or D_INVALIDATE or write to D_ADDR register when set. D_DRAINING bits are not valid while D_ERR_PEND is set or during transfers to the SCSI. In these cases, the D_DRAINING bits should be ignored. D_INVALIDATE - Bit 5 Setting this bit invalidates the D-FIFO. If D_ERR_PEND = 0 when D_INVALIDATE is set, all dirty data in the D-FIFO will first be drained to memory. If D_ERR_PEND=1 when D_INVALIDATE is set, all dirty data in the D-FIFO will be discarded. In addition to invalidating the D-FIFO, setting this bit causes D_ERR_PEND and D_TC to be reset. If D_EN_NEXT=1, D_A_LOADED and D_NA_LOADED will also be reset. D_RESET - Bit 7 D_RESET will remain active once written as a one until written as a zero, unless cleared by an SBus reset (sb_reset_ asserted). Setting D_RESET or asserting sb_reset_ will invalidate the D-FIFO, reset all SCSI interface state machines to their idle states, and assert the d_reset output for as long as D_RESET or sb_reset_ remains active. If D_ERR_PEND=0 when D_RESET is set, all dirty data in the D-FIFO will first be drained to memory. When this occurs, D_RESET must not be cleared until draining is complete, as indicated by D_DRAINING=00. If D_ERR_PEND=1 when D_RESET is set, no draining will take place and all dirty data in the D-FIFO will be discarded. If the CPU attempts a slave access to the SCSI while D_RESET or sb_reset_ is active, it willnot cause an error, but no data will actually be transferred since the d_reset output is being asserted throughout the access. D_EN_CNT & D_EN_NEXT - Bits 13 and 24 The D_EN_CNT and D_EN_NEXT control the modes of operation of the DMA Address register, Next Address register, Byte count and Next Byte count registers as follows: -------------------------------------------------------------------------- | D_EN_CNT | D_EN_NEXT | Mode | -------------------------------------------------------------------------- | 0 | 0 | Backward compatible with early SPARC stations. | -------------------------------------------------------------------------- | 0 | 1 | Illegal mode. Do not use. | -------------------------------------------------------------------------- | 1 | 0 | Backward compatible with early SPARC stations | | | | using byte count. Invalidate clears D_TC flag. | -------------------------------------------------------------------------- | 1 | 1 | Enables loading of D_NEXT_ADDR & D_NEXT_BCNT | | | | registers and auto-load of D_ADDR & D_BCNT on | | | | byte count expiration. Halt DMA on count | | | | expiration if D_NEXT_ADDR not loaded. | -------------------------------------------------------------------------- | NOTE: D_EN_CNT must always be set when D_EN_NEXT is set. | -------------------------------------------------------------------------- D_TC - Terminal Count - Bit 14 The D_TC bit will be set when D_BCNT makes a transition from 0x000001 to 0x000000. When it is set, an interrupt will be generated on the d_irq_ pin (if enabled by D_INT_EN and not disabled by D_TCI_DIS). When D_EN_NEXT=0, D_TC is cleared by D_INVALIDATE, D_RESET or sb_reset_. When D_EN_NEXT=1, D_TC can also be cleared by writing a 1 to it. D_BURST_SIZE - Bits 19:18 This field defines the sizes of SBus read and write bursts used by DMA2 for SCSI transfers. All reads from memory will be one size, either 4, 8, or 1 word (in 'no burst' mode). SBus writed to memory can be byte, half-word, or word, or one of the burst sizes given in the table. The DMA2 will always use the largest possible size for writes, which is dependent on D_BURST_SIZE and the number of bytes that need to be drained. Also, D_BURST_SIZE determines the draining level of the D-FIFO. When the D-FIFO has been filled with this amount of data, it will always be drained to memory. The sizes given in the following table are in SBus words. ------------------------------------------------------------------------------ | D_BURST_SIZE | Read Burst Size | Write Burst Sizes | D-FIFO Draining Level | ------------------------------------------------------------------------------ | D 00 | 4 words | 4 words | 4 words | ------------------------------------------------------------------------------ | 01 | 8 words | 4, 8 words | 8 words | ------------------------------------------------------------------------------ | 10 | no bursts AW | no bursts | 1 words | ------------------------------------------------------------------------------ | 11 | reserved | reserved | reserved | ------------------------------------------------------------------------------ | D = Default. | | AW = SBus reads are always 1 word in 'no burst' mode. | ------------------------------------------------------------------------------ D_TWO_CYCLE - Bit 21 Setting this bit modifies the timing of SCSI DMA sucha that one byte can be transferred every two SBus clocks, for a peak transfer rate of 10 MByte/sec in systems with a 20MHz sb_clk. This mode should only be used with SCSI controllers supporting this data rate, such as the NCR53C9X. This bit should ONLY be set when D_FASTER=0. D_FASTER - Bit 22 Setting this bit modifies the timing of SCSI DMA such that one byte can be transferred every three SBus clocks, for a peak transfer rate of 6.67 MByte/sec in systems with a 20 MHz sb_clk. This mode should only be used with SCSI controllers supporting this data rate, such as the NCR53C90A. This bit should ONLY be set when D_TWO_CYCLE=0. D_DMA_ON - Bit 25 Reads as 1 when (D_A_LOADED or D_NA_LOADED) & D_EN_DMA & NOT (D_ERR_PEND); otherwise reads as 0. When set, indicates that DMA2 is able to respond to DMA requests from the SCSI. D_A_LOADED & D_NA_LOADED - Bits 26 and 27. These bits define the validity of the values stored in the D_ADDR and D_NEXT_ADDR registers. D_A_LOADED is set when D_ADDR is written directly or when D_NEXT_ADDR is copied to D_ADDR, and is reset by D_RESET, (D_INVALIDATE & D_EN_NEXT), or D_BCNT expiring. D_NA_LOADED is seet when D_NEXT_ADDR is written. It is reset by D_RESET, D_EN_CNT=0, D_EN_NEXT=0, (D_INVALIDATE & D_EN_NEXT), or D_NEXT_ADDR being copied to D_ADDR. When the state is reached where a valid D_NEXT_ADDR has been loaded and the current D_ADDR has been marked as invalid (D_NA_LOADED = 1 & D_A_LOADED = 0), then the contents of the D_NEXT_ADDR register are copied to the D_ADDR register. The copy takes place on the same clock edge where the stated condition is sampled as true. So if address chaining has been set up to take place when the byte count expires, the actual sequence of events will be the following: First, D_A_LOADED will be cleared (on expiration of byte count). Second, the D_NEXT_ADDR will be copied to the D_ADDR register. These two events will probably be seen as one by software. Address Register (D_ADDR) & NEXT Address Register (D_NEXT_ADDR) -------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | -------------------------------------------------------------------------- | 31:0 | D_ADDR | Virtual Address Counter for SCSI access | R/W | | | | VA(31:0) | | -------------------------------------------------------------------------- | 31:0 | NEXT_ADDR | NEXT Address Register | W | -------------------------------------------------------------------------- The value in this register after a D_RESET is indeterminate. The Address Register is a 32-bit loadable counter which always points to the next byte that will be accessed by the SCSI, independent of which bytes in memory have been accessed by the DMA2. If the D_EN_NEXT (enable next address) bit in the D_CSR is set, then a write to the D_ADDR register will write to the D_NEXT_ADDR register instead. If D_EN_NEXT is set when the byte counter (D_BCNT) expires, and the D_NEXT_ADDR register has been written since the last time the byte counter expired, then the contents of D_NEXT_ADDR are copied into D_ADDR. If D_EN_NEXT is set when the byte counter (D_BCNT) expired, but the D_NEXT_ADDR register has not been written since the last time the byte counter expired, then DMA activity is stopped and DMA requests from the SCSI will be ignored until D_NEXT_ADDR is written, or D_EN_NEXT is cleared. (Also, the D_DMA_ON bit will read as 0 while DMA is stopped because of this). When DMA is re-enabled by writing to the D_NEXT_ADDR register, the contents of D_NEXT_ADDR are copied into D_ADDR before DMA activity actually begins. If the D_NEXT_ADDR register is written before the D_ADDR register has been written, the address written to D_NEXT_ADDR will immediately be copied into D_ADDR. When this occurs, it also causes the value in the D_NEXT_BCNT register to be copied into the D_BCNT register. This allows for a shortcut in loading both D_ADDR and D_NEXT_ADDR along with D_BCNT and D_NEXT_BCNT by writing the registers in the following sequence: D_NEXT_BCNT, D_NEXT_ADDR, D_NEXT_BCNT, D_NEXT_ADDR. When the first value is written into D_NEXT_ADDR, it is immediately copied into D_ADDR since D_ADDR hasn't been loaded yet. This causes the first value that was written into D_NEXT_BCNT to be copied into D_BCNT. The second values written into D_NEXT_BCNT and D_NEXT_ADDR then remain there as the actual next address and byte count. This allows the loading of both the current and next address and byte count registers without having to write the D_CSR to change the D_EN_NEXT bit in between. NOTE: A write to the D_ADDR register will invalidate the D-FIFO. A write to the D_NEXT_ADDR register does not have this effect. Byte Counter (D_BCNT) & NEXT Byte Counter (D_NEXT_BCNT) -------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | -------------------------------------------------------------------------- | 23:0 | D_BCNT | Byte COunt; counts down to 0, then sets | R/W | | | | the D_TC bit in the D_CSR | | -------------------------------------------------------------------------- | 23:0 | D_NEXT_BCNT| NEXT Byte Count Register | W | -------------------------------------------------------------------------- The value in this register after a D_RESET is indeterminate. When reading this register as a word, bits 31:24 will read as 0's. When enabled, the Byte Counter is decremented every time a byte is transferred between the DMA2 and the SCSI in a SCSI DMA cycle. It is decremented immediately after the byte has been transferred. It is not decremented on slave accesses to the SCSI or on transfers between the DMA2 and memory. If the D_EN_NEXT bit in the D_CSR is set, then a write to the D_BCNT register will write to the D_NEXT_BCNT register instead. Whenever the D_NEXT_ADDR register is copied into the D_ADDR register, the D_NEXT_BCNT register is copied into the D_BCNT register at the same time. If D_NEXT_ADDR is being copied into D_ADDR and D_NEXT_BCNT has not been written since the last time D_NEXT_BCNT was copied into D_BCNT, the last value that was written into D_NEXT_BCNT will again be copied into D_BCNT. This provides a shortcut in setting up consecutive DMA transfers of equal size from different addresses, in that D_NEXT_BCNT only needs to be written once as long as D_NEXT_ADDR is loaded for each successive transfer. If D_EN_NEXT is not set when D_BCNT expires (changes from 0x000001 to 0x000000), then DMA activity between the SCSI and the DMA2 will be stopped and the D_DMA_ON bit will read as 0 until D_ADDR is written. If D_EN_NEXT is set, then DMA will be stopped on D_BCNT expiration. NOTE: Loading D_BCNT with 0 will allow 2^24 bytes to be transferred before it expired. SCSI Test Control/Status Register (D_TST_CSR) The D_TST_CSR is a 32-bit R/W register internal to DMA2 provided for testability purposes. It is accessed as indicated in the DMA2 Internal Registers Address Map (Table 3-1). The read and write functions of the bits in the D_TST_CSR are deifned in the following table: -------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | -------------------------------------------------------------------------- | 31 | LD_TAG | Writing to 1 loads FIFO DMA address | W | | | | register (ADDR_TAG) with value in D_ADDR | | -------------------------------------------------------------------------- | 30 | REQ_OUT | Reads as 1 when FIFO is making a request | R | | | | for an SBus read or write. | | -------------------------------------------------------------------------- | 30 | RD_BURST | Writing to 1 initiates a DMA burst read | W | | | | from memory into FIFO from address in | | | | | ADDR_TAG. | | -------------------------------------------------------------------------- | 29 | WR_CNT | Writing to 1 loads FIFO CNT register with| W | | | | D_TST_CSR(5:0). | | -------------------------------------------------------------------------- | 28 | WRITE | Writing to 1 puts FIFO into 'WRITING' | R/W | | | | mode. Reads as 1 when FIFO in 'WRITING' | | | | | mode. | | -------------------------------------------------------------------------- | 27 | DRAIN | Reads as 1 if FIFO is draining. Writing | R/W | | | | to 1 forces FIFO to drain. | | -------------------------------------------------------------------------- | 26 | EMPTY | Reads as 1 if FIFO buffer is empty. | R | -------------------------------------------------------------------------- | 25 | FULL | Reads as 1 if FIFO buffer is full. | R | -------------------------------------------------------------------------- | 24 | LO_MARK | Reads as 1 if FIFO buffer has enough room| R | | | | for 1 Sbus read burst of data. | | -------------------------------------------------------------------------- | 23 | HI_MARK | Reads as 1 if FIFO contains enough data | R | | | | for 1 SBus write burst. | | -------------------------------------------------------------------------- | 5:0 | COUNT | Reads CNT register containing number of | R | | | | bytes stored in FIFO buffer. | | -------------------------------------------------------------------------- | 5:0 | COUNT | When WR_CNT=1, writes CNT register | W | | | | containing number of bytes stored in FIFO| | | | | buffer. | | -------------------------------------------------------------------------- NOTE: The D_TST_CSR is intended for diagnostic and test use only, and should never be written while a DMA transfer is active. Programming Notes To setup a transfer to/from the SCSI using DMA2 The transfer may be setup by first programming the internal byte count and address registers of the DMA2. But first, the software driver needs to ensure that no error bits are set in the D_CSR. It may do this by issuing a D_INVALIDATE and/or D_RESET command. Once this is done, the driver then programs the WRITE, D_INT_EN, D_EN_CNT, (D_FASTER), and D_TCI_DIS bits in the D_CSR. These map to the following usages: WRITE: determines direction of transfer D_EN_CNT: set to override the SCSI byte count register and use that of DMA2 D_FASTER: this should be set with every D_RESET D_TCI_DIS: set to disable interrupts upon byte count = 0 D_INT_EN: set to enable interrupts upon error conditions and byte count = 0 Next, the SCSI chip should be programmed with the appropriate data for the particular transfer. Finally, the ENA_DMA bit should be set. This bit acts as a gate such that the DMA2 will immediately begin to respond to SCSI requests for service. The transfer will now complete with one of three events: an error, in which case the driver must go poll the SCSI for status, an interrupt, for which the driver must provide service, or expiration of the byte count register. This last may be used in combination with the chaining feature presented in subsequent sections of this spec. To stop a transfer to/from the SCSI using DMA2 The driver may suspend transfers between the SCSI and DMA2 at any time by simply clearing the ENA_DMA bit. Note that memory accesses by the SBus side of the DMA2 chip are still possible even with this bit cleared. The transfer is easily restarted by again setting the ENA_DMA bit. Use of Internal Byte Counter with Next Address feature disabled When using the internal Byte Counter and the D_TC flag in the D_CSR with D_EN_NEXT = 0, it is necessary to perform the following procedure for correct operation: Load Byte Count into D_BCNT Load DMA address into D_ADDR Load Peripheral Device with relevant command(s) Load D_CSR with enables and direction bits (D_EN_DMA, D_EN_CNT, and WRITE) Data will be transferred as directed until the Byte Count expires, at which point the D_TC flag will be set in the D_CSR and an interrupt will be generated, if enabled. DMA will also be stopped at this time (D_DMA_ON will be cleared). DMA will remain stopped, independent of the value in D_EN_DMA, until D_ADDR is loaded with a new value. (NOTE: this implies that the interrupt service routine should clear D_EN_DMA before writing a new address to D_ADDR.) Once the CPU has serviced the interrupt and wishes to start another DMA operation it is necessary to proceed as follows: Issue a D_INVALIDATE command and then repeat the above procedure. (Clears D_TC bit of D_CSR) Use of Internal Byte Counter with Next Address feature enabled When using the internal Byte Counter, the D_TC flag in the D_CSR and the NEXT ADDRESS feature, it is necessary to perform the following procedure for correct operation: NOTE: This is a suggested procedure since several methods of programming the chip are possible. INITIALIZATION Initialization if the state of the chip is not defined such as after an error. Write Control register D_TCI_DIS, D_EN_DMA, D_EN_NEXT, D_RESET = 0 D_INVALIDATE, D_EN_CNT, D_INT_EN = 1 WRITE = value when read MULTIPLE BLOCK TRANSFERS To do a multiple block transfer with an interrupt after each block: Write Control register D_INT_EN, D_EN_DMA, D_EN_CNT, D_EN_NEXT = 1 D_TCI_DIS, D_INVALIDATE, D_RESET = 0 WRITE = value as read or desired Write D_BCNT with byte count of the first block. Write D_ADDR with the starting address of the first block. Set-up and start the SCSI chip to do its transfer. Write D_NEXT_BCNT with the byte count of the 'next' block. Loading of the D_NEXT_BCNT is optional because the initial loading of the D_BCNT also loads the next count register. Write D_NEXT_ADDR with the address of the 'next' block. The transfer of the first block is enabled and the transfer of the next block will happen automatically when Terminal Count is reached, i.e.: the next address and byte counts will be used. (This assumes the loading of the NEXT count and address occur before the first block transfer is complete.) INTERRUPT After each interrupt: Read D_CSR D_TC and D_DMA_ON should both = 1. If D_DMA_ON = 0 then, the D_NEXT_ADDR register did not get updated or there is an error pending, D_ERR_PEND. (It could also mean the DMA is not enabled, D_EN_DMA, or the next address feature is not enabled, D_EN_NEXT, but they were set = 1 so this should not be the case.) Write D_NEXT_BCNT with the byte count of the 'next' block. Loading of the D_NEXT_BCNT register is optional, buf if loaded, must be loaded before the D_NEXT_ADDR register. Write D_NEXT_ADDR with the address of the 'next' block. LAST BLOCK If no Terminal Count interrupt is desired after the last block is transferred: (because we expect an interrupt from the SCSI chip at the end of the transfer.) On interrupt of the next to last block: Read D_CSR D_TC and D_DMA_ON should both = 1. Write D_CSR D_TCI_DIS, INT_EN, D_EN_DMA, D_EN_CNT, D_EN_NEXT = 1 D_INVALIDATE, D_RESET = 0 Write = value as read or desired The D_NEXT_ADDR register is not loaded so the transfer will stop. NEXT TRANSFER The initialization for the next multi-block transfer is: Write D_CSR D_INT_EN, D_EN_DMA, D_EN_CNT, D_EN_NEXT = 1 D_TCI_DIS, D_INVALIDATE, D_RESET = 0 WRITE = value as read or desired This assumes the chip is in a known state because, if not, the write to the D_BCNT and D_ADDR registers may go to the NEXT registers (See INITIALIZATION). Write D_BCNT with byte count of the first block. Write D_ADDR with the starting address of the first block. Set-up and start the SCSI chip to do its transfer. Write D_NEXT_BCNT with the byte count of the 'next' block. Loading of the D_NEXT_BCNT is optional because the initial loading of the D_BCNT also loads the next count register. Write D_NEXT_ADDR with the address of the 'next' block. TAKING ADVANTAGE OF 'NEXT' FEATURE If an interrupt occurs and the 'next' address is not available, there is no room in the buffer or data is not available, the processor can take advantage of the fail-safe capability by not loading the D_NEXT_ADDR and the DMA will stop when the count goes to 0. After the 'next' address becomes known the processor must determine if the transfer of the current block has completed. If it has not, the processor should load the 'next' count and address to continue the transfer. If the transfer has completed, the processor should load the current count and address and the next count and next address to restart the transfer. NOTES: 1) There will be an interrupt generated when the count goes to zero. 2) The firmware must understand that if the transfer has stopped because the D_NEXT_ADDR was not loaded before the terminal count was reached, it is effectively loading the D_BCNT and D_ADDR registers, not the NEXT registers. This will enable the DMA to restart the transfer. 3) It is necessary to load the count before the address because the loading of the address register causes the restart of the transfer. Additional Notes Interrupts from the SCSI are visible as D_INT_PEND in the D_CSR. The D_INT_EN bit is provided to enable or disable the generation of an interrupt to the IU. If an error condition exists during a memory access, (this could be late errors, protection errors, time-outs etc.), the D_ERR_PEND bit will be set. This will cause an interrupt (if enabled) to the IU. Similarly, expiration of the Byte COunter will cause the D_INT_PEND bit to be set and an interrupt (if enabled). The D_ERR_PEND bit can only be cleared by a D_INVALIDATE or D_RESET command, or sb_reset. Software should never set the D_RESET or D_INVALIDATE bits in teh D_CSR or write to the D_ADDR register while the D_EN_DMA bit is set or while the D_DRAINING bits are set. TESTING the 'NEXT' REGISTERS When the processor writes to the D_BCNT and D_ADDR registers the data goes through the 'NEXT' registers. This 'feature' can be used to test the 'NEXT' registers since they can not be read directly. Bidirectional Parallel Port The parallel port consists of four 8-bit Parallel Port interface registers, three 16-bit COnfiguration registers, and a 64-byte FIFO. The parallel port can operate in programmed I/O mode or be DMA driven. The interface direction, timing and protocol is programmable to meet the wide variety of "Centronics" interfaces that exist on peripheral devices. Three functional blocks make up the interface: DMA Control, P-FIFO, and the parallel port register interface. The functional blocks, register sets, and operational modes are discussed below. Parallel Port DMA Parallel port DMA can operate in either a chained or unchained transfer mode. Mode selection, interrupt control and general DMA control is performed via the Parallel Port Control/Status Register (P_CSR). Transfer direction (to or from memory) is reflected in the P_CSR but is controlled via the Parallel Port Transfer Control Register (P_TCR). The operation of bothmodes is discussed in the following sections. Unchained DMA Transfers The unchained mode operates using a single address register and optionally the Byte Count Register. If the byte counter has been enabled by setting the P_EN_CNT bit of the P_CSR, the byte count will be decremented each time a byte is transferred to or from the parallel port data bus, p_data(7:0). When the byte count expires (changes from 0x000001 to 0x000000), the terminal count bit (P_TC) will be set, DMA will be halted, and an interrupt will be generated if enabled via P_INT_EN=1 and P_TCI_DIS=0. Unchained DMA transfers are terminated in one of two ways. If the byte counter expires (changes from 0x000001 to 0x00000), DMA will be halted, P_TC will be set P_A_LOADED will be reset, and P_DMA_ON will be cleared until a new DMA address is loaded into the P_ADDR register. Otherwise, the transfer can be terminated through software by clearing the P_EN_DMA bit of the P_CSR. In both cases, on termination of transfers from memory to the peripheral device the P-FIFO will be invalidated, and on termination of transfer from the peripheral device to memory all valid data in the P-FIFO will be drained to memory. Chained DMA Transfers Chained DMA transfers also use the address and byte count registers to perform transfers. In addition, they also use the NEXT address and NEXT byte count register set to accomplish the chaining of DMA transfers. DMA transfer chaining is enabled via the P_EN_NEXT and P_EN_CNT bits in the P_CSR. Note that use of the byte counter is essential to DMA chaining, as it is byte count expiration that initiates the loading of the NEXT address and NEXT byte count into the address and byte count registers. CHained DMA transfers are terminated in the following ways. If the byte counter expires (changes from 0x000001 to 0x000000) and DMA chaining has been disabled (P_EN_NEXT=0), DMA will be halted, P_TC will be set, P_A_LOADED will be reset, and P_DMA_ON will be cleared until a new DMA DMA address is loaded into the P_ADDR register, If the byte counter expires, DMA chaining is enabled (P_EN_NEXT=1), and the NEXT address/byte count is invalid (P_NA_LOADED=0), DMA will be halted until the NEXT register set has been written. Finally, the transfer can be terminated through software by clearing the P_EN_DMA bit of the P_CSR. Ina ll three cases, on termination of transfers from memory to the peripheral device the P-FIFO will be invalidated, and on termination of transfers from the peripheral device to memory all valid data in the P-FIFO will be drained to memory. NEXT Register Access The NEXT register set used for chaining can only be accessed indirectly. The P_EN_NEXT bit of the P_CSR defines whether register writes to the address/byte count registers access the address/byte counter registers or the NEXT address/byte count registers. When the P_EN_NEXT bit is set, all write accesses to the address/byte count register locations are actually writes to the NEXT registers. The NEXT registers shadow the counter registers. Note that the NEXT registers cannot be read directly. Two P_CSR bits pertain to the validity of the address and NEXT address registers. The P_A_LOADED bit indicates whether the address counter contains a valid address and the P_NA_LOADED indicates whether the NEXT address register contains a valid address. DMA Memory Clear The clearing of memory can be hardware assisted by setting the MEM_CLR and DATA_SRC bits of the Parallel Port Operation Configuration Register (P_OCR). The MEM_CLR bit specifies a DMA transfer to memory using the DATA_SRC bit as the data to be sourced. Once MEM_CLR has been set, the P_WRITE bit of the P_CSR will reflect the transfer direction to memory. Setting the P_EN_DMA bit will start the transfer. Either of the above DMA transfer methods can be used but in either case the byte counter must be enabled and used to control the transfer. When terminal count is reached and P_EN_NEXT is cleared the transfer will be terminated. When terminal count is reached and P_EN_NEXT is set but the NEXT address/byte count is invalid (P_NA_LOADED cleared), the transfer will be suspended until the NEXT register set has been written. Interrupts on P_TC operate according to the transfer mode selected. Parallel Port DMA Registers All Parallel Port DMA registers are accesses as 32 bit registers. However, not all registers have 32 significant bits. The mnemonics for all Parallel Port registers are all preceded by "P". The Addr field of the register definitions correspond to SBus physical address bits 4:0. Additionally, to access these registers the pa(x, y, z) physical address bits must be 101, respectively. PP DMA Address Register (P_ADDR) and NEXT Address Register (P_NEXT_ADDR) -------------------------------------------------------------------------- | Addr | Bits | Description | Size | Type | -------------------------------------------------------------------------- | 04 | 31:0 | PP DMA Address Register (P_ADDR). | 32 bit | R/W | -------------------------------------------------------------------------- | 04 | 31:0 | PP DMA NEXT Address Reg (P_NEXT_ADDR). | 32 bit | W | -------------------------------------------------------------------------- This 32-bit R/W register contains the virtual address for Parallel Port DMA transfers. It is implemented as a 32-bit loadable counter which points to the next byte that will be accessed via the Parallel Port. If the P_EN_NEXT (enable next address) bit in the P_CSR is set, then a write to the P_ADDR register will write to the P_NEXT_ADDR register instead. If P_EN_NEXT is set when the byte counter (P_BCNT) expires, and the P_NEXT_ADDR register has been written since the last time the byte counter expired, then the contents of P_NEXT_ADDR are copied into P_ADDR. If P_EN_NEXT is set when the byte counter (P_BCNT) expires, but the P_NEXT_ADDR register has not been written since the last time the byte counter expired, then DMA activity is stopped and DMA requests from the Parallel Port will be ignored until P_NEXT_ADDR is written or P_EN_NEXT is cleared. (Also, the P_DMA_ON bit will read as 0 while DMA is stopped because of this). When DMA is re-enabled by writing to the P_NEXT_ADDR register, the contents of P_NEXT_ADDR are copied into P_ADDR before DMA activity actually begins. NOTE: A write to the P_ADDR register will invalidate the P-FIFO. A write to the P_NEXT_ADDR register does not have this effect. PP DMA Byte COunt Register (P_BCNT) & NEXT Byte Count (P_NEXT_BCNT) -------------------------------------------------------------------------- | Addr | Bits | Description | Size | Type | -------------------------------------------------------------------------- | 08 | 23:0 | PP DMA Byte Count (P_BCNT) | 32 Bit | R/W | -------------------------------------------------------------------------- | 08 | 23:0 | PP DMA NEXT Byte Count (P_NEXT_BCNT) | 32 Bit | W | -------------------------------------------------------------------------- This register is implemented as a 24 bit down counter. When readint this register as a word, bits 31:24 will read as 0's. The register should be loaded with a 24 bit byte count which, if enabled via the P_EN_CNT bit in the P_CSR, will be decremented every time a byte is transferred between the DMA2 and whatever external device is connected to the parallel port. Transition of this register to zero, Terminal Count (P_TC), will generate an interrupt if not disabled via the P_TCI_DIS bit of the P_CSR. If the P_EN_NEXT bit in the P_CSR is set, then a write to the P_BCNT register will write to the P_NEXT_BCNT register instead. Whenever the P_NEXT_ADDR register is copied into the P_ADDR register, the P_NEXT_BCNT register is copied into the P_BCNT register at the same time. If P_NEXT_ADDR is being copied into P_ADDR and P_NEXT_BCNT has not been written since the last time P_NEXT_BCNT was copied into P_BCNT, the last value that was written into P_NEXT_BCNT will again be copied into P_BCNT. This provides a shortcut in setting up consecutive DMA transfers of equal size from different addresses, in that P_NEXT_BCNT only needs to be written once as long as P_NEXT_ADDR isloaded for each successive transfer. If P_EN_NEXT is not set when P_BCNT expires (changes from 0x000001 to 0x000000), then Parallel Port DMA activity will be stopped and the P_DMA_ON bit will read as 0 until P_ADDR is written. If P_EN_NEXT is set, then DMA will be stopped on P_BCNT expiration. NOTE: Loading P_BCNT with 0 will allow 2^24 bytes to be transferred before it expires. PP Test Control/Status Register (P_TST_CSR) The P_TST_CSR is a 32-bit R/W register internal to DMA2 which provides testability functions for the parallel port interface. It is accessed as indicated in the DMA2 Internal Registers Address Map (Table 3-1). The functionality of the P_TST_CSR is identical to the D_TST_CSR, except that it affects the P-FIFO instead of the D-FIFO. Parallel Port COntrol/Status Register (P_CSR) This register provices DMA status and control information for the Parallel Port. ADDR=0, Size=32 Bits --------------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | --------------------------------------------------------------------------- | 0 | P_INT_PEND | Set when a PP DMA or PP Control interrupt| R | | | | is pending or when P_TC set and P_TCI_DIS| | | | | not set. | | --------------------------------------------------------------------------- | 1 | P_ERR_PEND | Set when an interrupt is pending due to | R | | | | an SBus error condition. | | --------------------------------------------------------------------------- | 3:2 | P_DRAINING | Both bits set when the P-FIFO is draining| R | | | | to memory, otherwise both bits are 0. | | --------------------------------------------------------------------------- | 4 | P_INT_EN | When set, enables sb_p_irq to become | R/W | | | | active when either P_INT_PEND or | | | | | P_ERR_PEND are set. | | --------------------------------------------------------------------------- | 5 | P_INVALIDATE| When set, invalidates the P-FIFO. Resets | W | | | | itself. Reads as 0. | | --------------------------------------------------------------------------- | 6 | P_SLAVE_ERR | Set on slave access size error to a PP | R/W* | | | | register. Reset by P_RESET, P_INVALIDATE| | | | | or writing to 1. | | --------------------------------------------------------------------------- | 7 | P_RESET | When set, acts as a hardware reset to | R/W | | | | the Parallel Port only. | | --------------------------------------------------------------------------- | 8 | P_WRITE | DMA Direction. 1=To memory; 0=From | R | | | | memory. | | --------------------------------------------------------------------------- | 9 | P_EN_DMA | When set, enables DMA transfers to/from | R/W | | | | the PP. | | --------------------------------------------------------------------------- | 12:10 | -- | Unused. Reads as 0. | R | --------------------------------------------------------------------------- | 13 | P_EN_CNT | When set, enables the PP byte counter to | R/W | | | | be decremented. | | --------------------------------------------------------------------------- | 14 | P_TC | Terminal count. Set when byte count | R/W* | | | | expires. Reset on write of 1 if | | | | | P_EN_NEXT=1. | | --------------------------------------------------------------------------- | 17:15 | -- | Unused. Reads as 0. | R | --------------------------------------------------------------------------- | 19:18 | P_BURST_SIZE| Defines sizes of SBus read and write | R/W | | | | bursts for PP transfers. | | --------------------------------------------------------------------------- | 20 | P_DIAG | When set, disables draining and resetting| R/W | | | | of P-FIFO on loading of P_ADDR register. | | --------------------------------------------------------------------------- | 22:21 | -- | Unused. Reads as 0. | --- | --------------------------------------------------------------------------- | 23 | P_TCI_DIS | When set, disables P_TC from generating | R/W | | | | an interrupt. | | --------------------------------------------------------------------------- | 24 | P_EN_NEXT | When set, enables DMA chaining and | R/W | | | | NEXT address/byte count auto-load | | | | | mechanism. P_EN_CNT must also be set. | | --------------------------------------------------------------------------- | 25 | P_DMA_ON | DMA On. When set, indicates that DMA | R | | | | transfers are not disabled due to any | | | | | hardware or software condition. | | --------------------------------------------------------------------------- | 26 | P_A_LOADED | Set when the contents of the address | R | | | | and byte count are considered valid | | | | | during chained transfers. | | --------------------------------------------------------------------------- | 27 | P_NA_LOADED | Set when NEXT Address and byte count | R | | | | registers have been written but have | | | | | not been used for chaining. | | --------------------------------------------------------------------------- | 31:28 | P_DEV_ID | Device ID = 1010 | R | --------------------------------------------------------------------------- | *R/W bits are readable and cleared by writing to logic 1. | --------------------------------------------------------------------------- The RESET state of this register is as follows: P_ERR_PEND=P_INT_EN=P_INVALIDATE=P_SLAVE_ERR=P_RESET= P_WRITE=P_EN_DMA=P_EN_CNT=P_TC=P_BURST_SIZE=P_TCI_DIS= P_EN_NEXT=P_DMA_ON=P_A_LOADED=P_NA_LOADED=0. P_INT_PEND Interrupt pending is the logical OR of the following enabled PP interrupt sources: (P_TC & !P_TCI_DIS), DS_IRQ, ACK_IRQ, BUSY_IRQ, ERR_IRQ, PE_IRQ, SLCT_IRQ. P_ERR_PEND Error pending will be set due to an SBus error acknowledge or an SBus late error. It indicates an SBus error condition. PP DMA is stopped (P_DMA_ON=0) when this bit is set. This bit can be resetby setting P_INVALIDATE or P_RESET. P_DRAINING When P-FIFO is draining to memory, both bits are set. Do not assert P_RESET or P_INVALIDATE or write to the P_ADDR register when set. P_DRAINING bits are not valid while P_ERR_PEND is set and should be ignored. P_INVALIDATE Setting this bit invalidates the P-FIFO. If P_ERR_PEND=0 when P_INVALIDATE is set, all dirty data in the P-FIFO will first be drained to memory. If P_ERR_PEND=1 when P_INVALIDATE is set, all dirty data in the P-FIFO will be discarded. In addition to invalidating the P-FIFO, setting this bit causes P_ERR_PEND and P_TC to be reset. If P_EN_NEXT=1, P_A_LOADED and P_NA_LOADED will also be reset. P_RESET This bit functions as a hardware reset to the parallel port. It will remain active once written to one until written to zero, unless cleared by an SBus reset (sb_reset_ asserted). Setting P_RESET or asserting sb_reset_ will invalidate the P-FIFO and reset all parallel port interface state machines to their idle states. If P_ERR_PEND=0 when P_RESET is set, all dirty data in the P-FIFO will first be drained to memory. When this occurs, P_RESET must not be cleared until draining is complete, as indicated by P_DRAINING=00. If P_ERR_PEND=1 when P_RESET is set, no draining will take place and all dirty data in the P-FIFO will be discarded. P_WRITE This read only bit reflects the direction for DMA transfers. It is a logical OR of the DIR bit of the Parallel Control Register (P_CR) and the MEM_CLR bit of the parallel operation control register (P_OCR). P_TC This bit will be set when the byte counter (P_BCNT) transitions from 0x000001 to 0x000000. This will generate an interrupt if enabled by P_INT_EN and not disabled by P_TCI_DIS. During unchained transfers, P_TC causes P_DMA_ON to be reset. When P_EN_NBEXT=0, P_TC is cleared by P_INVALIDATE, P_RESET, or sb_reset_. When P_EN_NEXT=1, P_TC can also be cleared by writing a 1 to it. P_BURST_SIZE This field defines the sizes of SBus read and write bursts used by the DMA2 for parallel port transfers. All reads from memory will be one size, either 4, 8, or 1 word (in 'no burst' mode). SBus writes to memory can be byte, half-word, word, or one of the burst sizes given in the table. The DMA2 will always use the largest possible size for writes, which is dependent on P_BURST_SIZE and the number of bytes that need to be drained. Also, P_BURST_SIZE determines the draining level of the P-FIFO. When the P-FIFO has been filled with this amount of data, it will always be drained to memory. The sizes given in the following table are in SBus words. ------------------------------------------------------------------------------ | P_BURST_SIZE | Read Burst Size | Write Burst Sizes | P-FIFO Draining Level | ------------------------------------------------------------------------------ | 00 | 4 words | 4 words | 4 words | ------------------------------------------------------------------------------ | 01 | 8 words | 4, 8 words | 8 words | ------------------------------------------------------------------------------ | 10 | no bursts | no bursts | 1 word | ------------------------------------------------------------------------------ | 11 | reserved | reserved | reserved | ------------------------------------------------------------------------------ P_DMA_ON When set, indicates that DMA2 is able to respond to Parallel Port DMA requests. Reads as 1 when (P_A_LOADED or P_NA_LOADED) & P_EN_DMA & NOT(P_ERR_PEND); otherwise reads as 0. Parallel Port FIFO (P-FIFO) Operation Between the Parallel Port and the SBus interface is a 64-byte FIFO (P-FIFO). This FIFO is bypassed for slave accesses to the Parallel Port registers. Consistency control ensures that all data written by the external device gets to main memory in a deterministic manner, and is handled completely in hardware. One of the consistency control mechanisms used on transfers to memory is draining of all P-FIFO data upon the access of any parallel port register. The P-FIFO is implemented using the same logic block as the D-FIFO, and thus has identical functionality internally. Refer to the SCSI section for detailed descriptions on how the FIFO handles transfers to and from memory, invalidation conditions, and memory errors. The conditions that cause data in the P-FIFO to be drained to memory are slightly different than those for the D-FIFO, and are as follows: 1) 4, 16 or 32 bytes (depending on P_BURST_SIZE) have been written into the P-FIFO. 2) The P_INT_PEND bit in the P_CSR is set. 3) The CPU does a slave write to a Parallel port internal register other than the P_TST_CSR (writing P_ADDR does not cause draining if P_DIAG is set). 4) The P_RESET or P_INVALIDATE bit in the P_CSR is set. 5) The P_ADDR register is loaded from P_NEXT_ADDR when P_DIAG is not set. None of these conditions will cause draining if P_ERR_PEND=1, indicating that a memory error has occurred. If Condition 4 or 5 occurs when P_ERR_PEND=1, the P-FIFO will be invalidated and all dirty data discarded. Bidirectional Parallel Port Interface The parallel port can operate unidirectionally or bi-directionally in either a programmed I/O mode or in a DMA mode. The hardware interface can be configured to operate with a wide range of devices through the following mechanisms: - Bidirectional signal configuration for the interface control signals-data strobe, acknowledge, and busy. Each control signal can be individually configured as a unidirectional or as a bidirectional signal. - Programmable pulse widths for all generated signals and programmable data setup time for data transfers. - Programmable protocol definition for all combinations of acknowledge and busy handshaking. This interface configuration capability will allow operation over a wide range of data transfer rates and protocol definitions. The operational modes and a description of each of the individual registers are presented below. DMA Mode DMA mode automates the data transfer over the port as has been discussed in the previous sections on PP DMA. Since no software intervention is required for data transfer, the interface protocol and timing required must be programmed via the configuration registers. DMA transfers are initiated/enabled by setting the P_EN_DMA bit of the P_CSR. The operation of the interface is dependent on the direction of transfer and the protocol selected as described below. Unidirectional Operations (Transfers To the Peripheral Device) This mode of operation is the "Centronics" implementation of a unidirectional parallel port. Operation of the parallel port in this mode requires the direction control bit (DIR) of the Transfer Control Register (TCR) to be 0. Timing variations are handled via the DSS (data setup and ata strobe) and DSM (data strobe width) bits of the Hardware COnfiguration Register. The timebase for programmability is the SBus clock. The DSS parameter (7 bits) can be programmed from a minimum of 0 SBus clocks to 127 SBus clocks in steps of one SBus clock. The DSW parameter (7 bits) is also programmed ins teps of one SBus clock, however, when DSW=0, 1, 2, or 3, data strobe width is defined as three SBus clocks. That is, the minimum data strobe width is three SBus clocks. The following table shows the nominal range of programmability for different SBus clock speeds. ------------------------------------------------------------ | SBus Clock | DSS | DSW | ------------------------------------------------------------ | 16.67 MHz | 0 - 7.62 us | 180.0 ns - 7.62 us | ------------------------------------------------------------ | 20 MHz | 0 - 6.35 us | 150.0 ns - 6.35 us | ------------------------------------------------------------ | 25 MHz | 0 - 5.08 us | 120.0 ns - 5.08 us | ------------------------------------------------------------ The desired handshake protocol can be selected using the ACK_OP (acknowledge operation) and BUSY_OP (busy operation) bits of the Operations COnfiguration Register (OCR). The function of these bits is defined as follows: ACK_OP 1 = Handshake complete with receipt of p_ack. 0 = p_ack is ignored BUSY_OP 1 = Handshake complete with receipt of p_bsy_. 0 = p_bsy_ is not used for handshaking. These two bits allow selection of one of four possible protocols, however only three of these protocols make sense and are valid selections. The case of ACK_OP=BUSY_OP=1, is not supported. For all protocol selections, if p_bsy_ is active, further data transfers will not occur until p_bsy_ is negated. The following table summarizes the protocol definitions for transfers to the peripheral device: ------------------------------------------------------------ | BUSY_OP | ACK_OP | Protocol Definition | ------------------------------------------------------------ | 0 | 0 | No handshaking occurs. | ------------------------------------------------------------ | 0 | 1 | Acknowledge is required for each byte | | | | transferred. | ------------------------------------------------------------ | 1 | 0 | p_bsy_ is used as acknowledge and is | | | | required for each byte transferred. | | | | ack is ignored. | ------------------------------------------------------------ | 1 | 1 | Invalid. | ------------------------------------------------------------ The transfer modes are shown and discussed in the following sections. No Handshake (BUSY_OP=0, ACK_OP=0) Data transfers are controlled by the use of p_d_strb and optionally p_bsy_. There is no acknowledge in this mode and p_ack is a don't care. p_bsy_ is used to gate further transfers when the peripheral device cannot receive another byte of data. p_bsy_ is sampled before data strobe becomes active and after data strobe becomes inactive, to insure that a data transfer is not attempted while the device is busy. In this mode, which provides the fastest transfer of data over the interface, the fastest cycle time is six SBus clocks per byte. This transfer time is arrived at as follows: DSS=0, DSW=3 (minimum width of DSW is three SBus clocks), and thress SBus clocks between consecutive data strobes. This assumes that p_bsy_ is not asserted during the transfer cycle. Refer to the following data transfer diagram: (...) Handshake with Ack (BUSY_OP=0, ACK_OP=1) Data transfers are controlled by the use of p_d_strb, p_ack, and optionally p_bsy_. p_ack is required for each byte transferred. If p_bsy_ is active at the end of the cycle, further data transfers will be gated until p_bsy_ becomes inactive. If p_bsy_ is not present then data transfers will proceed. p_bsy_ is also sampled immediately before p_d_strb is generated to insure that a data transfer is not attempted while the device is busy. Refer to the following data transfer diagram: (...) Handshake with Busy (ACK_OP=0, BUSY_OP=1) Data transfers are controlled by the use of p_d_strb and p_bsy_. p_ack is a don't care in this mode. p_bsy_ is required as an acknowledge after p_d_strb and will gate any further data transfers while it is active. p_bsy_ is also sampled immediately before p_d_strb is generated to insure that a data transfer is not attempted while the device is busy. Refer to the following data transfer diagram: (...) Bidirectional Operation Bidirectional data transfer over the parallel port can be accomplished by the use of either of two master/slave protocols. the "master-write" protocol or the "master read/write" protocol. The IBM implementation of a bidirectional parallel port uses the "master write" protocol in which the master always writes data to the slave and when the direction of data transfer needs to be reversed, mastership is exchanged. The Xerox implementation uses the "master read/write" protocol where the data transfer is performed in either direction under control of the fixed master. The parallel port will operate as either master or slave when configured for master write protocol, and only as the master when configured for the master read/write protocol. The selection of one of these bidirectional transfer methods is accomplished indirectly through the specification of the bidirectional nature of the data strobe signal. Since in both methods data strobe resides with the master, a bidirectional data strobe implies the IBM "master write" scheme and fixed data strobe (output only) implies the Xerox "master read/write" scheme. The interface control signals - data strobe, acknowledge, and busy are individually configurable as bidirectional or unidirectional pins. The bidirectional signal configuration bits are locatd in the Operation Configuration Register. The function of the bits are as follows: DS_SEL 1 = Data strobe is bidirectional. Master write transfer protocol is selected. ACK_DSEL 1 = p_ack is bidirectional. 0 = p_ack is fixed as an input. BUSY_DSEL 1 = p_bsy_ is bidirectional. 0 = p_bsy_ is fixed as an input. To allow external driver/receiver connection, each of these control signals and the data bus has a corresponding direction control pin. The DIR bit of the Transfer Control Register is used to switch the direction of the data bus and the pins that have been configured as bidirectional. The state of the DIR bit is reflected on the p_d_dir_ pin for external transceiver control and direction control communication to the attached device. While DIR=0, all pins remain in their unidirectional sense which is defined to be consistent with the unidirectional parallel port as follows: ------------------------------------------ | Signal | I/O | Dir_Pin | State | ------------------------------------------ | p_d_strb | O | p_ds_dir | 1 | ------------------------------------------ | p_ack | I | p_ack_dir_ | 0 | ------------------------------------------ | p_bsy_ | I | p_bsy_dir_ | 0 | ------------------------------------------ | p_data | O | p_d_dir_ | 1 | ------------------------------------------ When DIR is set to 1, the pins configured as bidirectional change direction and their corresponding direction control pins are set accordingly. Note that the input status pins (err, slct, pe) which are readable in the Input Register are not configurable. They are fixed as inputs. Similarly, the output pins (p_afxn, p_init, p_slct_in) of the Output register are fixed as outputs. The transfer modes are shown and discussed in the following sections. Master Write Protocol, Slave Operation This section describes the parallel port operation as a slave when it is configured for master write protocol (DS_DSEL=1). Operation as a master is the same as is described in the Unidirectional Operation section. In this mode, acknowledge and/or busy can be generated in response to a data strobe. The width of the p_ack pulse can be defined using the DSW bits of the hardware configuration register. The p_bsy_ hold time and p_ack positioning after the trailing edge of data strobe are defined using the DSS bits. However note that in thismode, DSS has a tolerance of +3 to 4 SBus clocks, due to synchronization delays. The nominal programmability range is the same as was specified in the Unidirectional Operation section. The ACK_OP and BUSY_OP bits are used to specify handshake protocol. The function of thebits take on a new meaning when the parallel port is a slave. ACK_OP 1 = Generate p_ack in response to a data strobe. 0 = p_ack is not generated. p_ack is held in an inactive state. BUSY_OP 1 = Generate p_bsy_, as an acknowledge, in response to data strobe. 0 = p_bsy_ is not generated for each byte transferred, but is asserted as required. These two bits allow selection of one of four ppossible handshake protocols. The following table summarizes the protocol definitions for transfers to the parallel port from the peripheral device. ------------------------------------------------------------------ | BUSY_OP | ACK_OP | Protocol Definition | ------------------------------------------------------------------ | 0 | 0 | No handshaking occurs. | ------------------------------------------------------------------ | 0 | 1 | Acknowledge is generated for each byte | | | | transferred. | ------------------------------------------------------------------ | 1 | 0 | p_bsy_ is generated as an acknowledge for | | | | each byte transferred. p_ack remains | | | | inactive. | ------------------------------------------------------------------ | 1 | 1 | Both p_bsy_ and p_ack are generated for each| | | | byte transferred. | ------------------------------------------------------------------ For all protocol selections, p_bsy_ will become active if one of the following conditions occur: the P_DMA_ON bit is reset indicating DMA cannot proceed; or the P-FIFO is unable to accept more data. Internally, p_bsy_ will always be generated for these conditions. However, if the p_bsy_ pin is not configured as an output it will not be driven and the external interface will not be able to detect the busy condition. In this case data could be lost. Ina ll cases if p_bsy_ is asserted it will have the following timing characteristics: (...) The transfer modes are shown and discussed in the following sections: No Handshakes (BUSY_OP=0, ACK_OP=0) No handshake signals are generated in this mode. If p_ack is configured as an output it will remain low or inactive. p_bsy_ will be generated as required to gate further transfers but not as a handshake signal. The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=X, BUSY_DSEL=1. If p_ack is configured as an output it will remain low or inactive. The configuration of p_bsy_ as an output is suggested to avoid potential data loss. Reference the parallel port timing section for detailed timing requirements for this mode. Handshake with Ack (BUSY_OP=0, ACK_OP=1) Data transfers are acknowledged using p_ack. The position of p_ack relative to the trailing edge of data strobe is set using DSS. Note that in this mode, the actual positioning of p_ack will be DSS plus 3 to 4 SBus clocks, due to synchronization delays. The width of p_ack is set using DSW. p_bsy_ will be generated as required to gate further transfers but not as a handshake signal. The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=1, BUSY_DSEL=1. The configuration of p_bsy_ as an output is suggested to avoid potential data loss. Refer to the following data transfer diagram: (...) Handshake with Busy (BUSY_OP=1, ACK_OP=0) Data transfers are acknowledged using p_bsy_. p_bsy_ will be generated off of the leading edge of p_d_strb and will remain active for the period specified by DSS (plus 3 to 4 SBus clocks) beyond the end of p_d_strb. The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=X, BUSY_DSEL=1. The configuration of p_ack as an input will not hinder the operation of the interface as far as handshaking is concerned. If p_ack is configured as an output it will remain low or inactive. Refer to the following data transfer diagram: (...) Handshake with Ack and Busy (BUSY_OP=1, ACK_OP=1) Both p_ack and p_bsy_ are generated in response to a data strobe. p_bsy_ will be generated off of the leading edge of p_d_strb and will remain active for three SBus clocks beyond the end of p_ack. The position of p_ack relative to the trailing edge of data strobe is defined by DSS (again DSS has a tolerance of +3 to 4 SBus clocks). The width of p_ack is set using DSW. The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=1, BUSY_DSEL=1. Reference the following data transfer diagram: (...) Master Read/Write Protocol (Xerox Mode) This section describes the parallel port operation while master read cycles are performed. Operation while master write cycles are performed is the same as is described in the Unidirectional Operation section. Data transfer for master read cycles is accomplished by the master generating a data strobe (request for data) with no data present on the p_data bus. The peripheral responds by placing data on the p_data bus and generating a p_ack which functions as a strobe. Only one handshake protocol is valid for master read cycles. It is described below. Handshake with Ack (BUSY_OP=0, ACK_OP=1) Data is transferred to the parallel port by the use of p_ack. p_d_strb width is defined by DSW. DSS is used to define the required interval from p_ack to the next p_d_strb. p_bsy_ will gate further data transfers if present. The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=0, ACK_DSEL=0, BUSY_DSEL=0. Refer to the following data transfer diagram: (...) Programmed I/O Mode Programmed I/O mode is intended to allow the parallel port to operate primarily under software control. Data latching, interrupt and busy generation are performed in hardware as required. The following two sections describe operation for transfers to and from the peripheral device. PIO on Transfers To the Peripheral Device For transfers to the peripheral device, all signals are under the control of software. There is no hardware assist other than interrupt generation. PIO on Transfers From the Peripheral Device The two modes of bidirectional operation previously discussed are supported with hardware assisted data latching. The bidirectional select bits (DS_DSEL, ACK_DSEL, BUSY_DSEL) should be set according to the desired configuration. The handshake protocol bits (ACK_OP, BUSY_OP) have no function in PIO mode. During operation as a slave under the master write protocol (DS_DSEL=1, DIR=1), data is sampled and latched once data strobe has been detected. p_bsy_ becomes active at the same time that data is latched and must be made inactive under software control. During operation under master read/write protocol (DS_DSEL=0, DIR=1), master reads are assisted by sampling and latching the data once p_ack has been detected. p_bsy_ is not generated in this mode. Bidirectional Parallel Port Registers The parallel port register set consists of two 16-bit configuration registers, four 8-bit parallel port interface registers, and one 16-bit interrupt control register. The two 16-bit configuration registers can be accessed as individual 16 bit registers or as a word aligned pair. Similarly, the four 8-bit registers can be accessed as 8-bit registers, 16-bit halfword aligned pairs, or as one 32-bit register. The Addr field of the register definitions corresponds to SBus physical address bits 4:0. Additionally, to access these registers the pa(x, y, z) physical address bits must be 101, respectively. Parallel Port Configuration Registers Hardware Configuration Register (P_HCR) This 16-bit read/write register is used to specify the value of the two programmable timers. Reset value of this register is unknown, except the TEST bit which is reset to a 0. ADDR=10, Size=16 Bit ------------------------------------------------------------ | Bit | Mnemonic | Description | Type | ------------------------------------------------------------ | 6:0 | DSS | Data setup before data strobe in | R/W | | | | increments of 1 SBus clock. | | ------------------------------------------------------------ | 7 | --- | Unused. Reads as 0. | RO | ------------------------------------------------------------ |14:8 | DSW | Data strobe width in increments | R/W | | | | of 1 Sbus clock. | | ------------------------------------------------------------ | 15 | TEST | Test bit which when set, allows | R/W | | | | the buried counters to be read. | | ------------------------------------------------------------ DSS Data setup to data strobe. This 7 bit quantity is used to define several different timing specificaions for the interface. The contents of this field of the register are used to load a hardware timer whose timebase is the SBus clock. The programmability range is from a minimum of 0 SBus clocks to 127 SBus clocks. Bit 0 is the lsb and bit 6 is the msb. The sections on unidirectional and bidirectional transfers should be referenced for detailed information on the use of this timer. DSW Data strobe width. This 7 bit quantity is used to define data strobe and acknowledge pulse widths for the interface. The contents of this field of the register are used to load a hardware timer whose timebase is the SBus clock. The programmability range is from a minimum of 3 SBus clocks to 127 SBus clocks. In the case of the value being 0, 1, 2, or 3, the timer will be loaded with a value of 3. Bit 8 is the lsb and bit 14 is the msb. For detailed information on the use of this timer, refer to the sections on unidirectional and bidirectional transfers. Operation Configuration Register (P_OCR) This 16-bit read/write register is used to specify the operation of the interface. Bidirectional specification of the control signals (p_d_strb, p_ack, p_bsy_), handshake protocol, memory clear and diagnostic mode are defined in this register. The detailed function of the bits is described following the table. Reset value of this register is all bits 0, except DS_DSEL & IDLE, which are reset to 1, and bit 1, which always reads as 1. ADDR=12 Size=16 Bit ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 0 | --- | Reserved | R/W | ---------------------------------------------------------------------- | 1 | --- | Reserved. Reads as 1. | RO | ---------------------------------------------------------------------- | 2 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- | 3 | IDLE | Reads as one when the PP data transfer | RO | | | | state machines are idle. | | ---------------------------------------------------------------------- | 4 | --- | Unused Reads as 0. | RO | ---------------------------------------------------------------------- | 5 | --- | Unused Reads as 0. | RO | ---------------------------------------------------------------------- | 6 | --- | Unused Reads as 0. | RO | ---------------------------------------------------------------------- | 7 | SRST | When set, resets the parallel port. | R/W | | | | Must be reset by software. | | ---------------------------------------------------------------------- | 8 | ACK_OP | Acknowledge operation. | R/W | ---------------------------------------------------------------------- | 9 | BUSY_OP | Busy operation. | R/W | ---------------------------------------------------------------------- | 10 | EN_DIAG | When set, enables diagnostic mode. | R/W | ---------------------------------------------------------------------- | 11 | ACK_DSEL | Acknowledge bidirectional select. | R/W | | | | When set, ack_ is bi-dir. | | ---------------------------------------------------------------------- | 12 | BUSY_DSEL | Busy bidirectional select. When set, | R/W | | | | p_bsy_ is bi-dir. | | ---------------------------------------------------------------------- | 13 | DS_DSEL | Data Strobe bidirectional select. | R/W | | | | When set, p_d_strb is bi-dir. | | ---------------------------------------------------------------------- | 14 | DATA_SRC | Data source for memory clear operation.| R/W | ---------------------------------------------------------------------- | 15 | MEM_CLR | When set, enables memory clear. | R/W | ---------------------------------------------------------------------- IDLE When this bit is set, it indicates that the parallel port data transfer machines are in their idle states. The state machines should be idle when changing direction and/or configuring operational modes and when enabling a memory clear operation. SRST Setting this bit will place the parallel port data transfer state machines and programmable timers into reset. It will not reset any of the parallel port registers. This bitmust be reset by software. ACK_OP Used to specify the handshake protocol to be used on the interface. The meaning of this bit differs depending on the direction of transfer. Refer to the sections on unidirectional andbidirectional transfers for detailed information on this bit. The general definition is as follows: 1 = Handshake using p_ack. 0 = p_ack is inactive. BUSY_OP Used to specify the handshake protocol to be used on the interface. The meaning of this bit differs depending on the direction of transfer. Refer to the sections on unidirectional and bidirectional transfers for detailed information on this bit. The general definition is as follows: 1 = Handshake performed using p_bsy_. 0 = p_bsy_ is not used for handshaking. EN_DIAG Setting this bit enables diagnostic mode which does three things: 1) Bits 0-2 of the output register are gated on to bits 0-2 of the input register. This allows testing of the data path and the interrupt generation logic. 2) The internal DS, ACK, and BUSY latch bits drive the internal DS_IRQ and ACK_IRQ, and BUSY_IRQ interrupt generation logic. 3) When reading the DS, ACK, and BUSY bits of the Transfer Control Register, the read data comes from the internal latches instead of the external pins. During diagnostic mode, if the DS or ACK bits are configured as outputs, the output pins will be gated to an inactive level. The BUSY-output will be driven active and the DIR output will be latched in its current state. ACK_DSEL This bit is a bidirectional select for the p_ack signal. When reset, p_ack is fixed as an input. When set, p_ack is a bidirectional signal. The p_ack_dir_ pin will reflect the direction of p_ack. The switching of direction is controlled by the DIR bit of the Transfer Control Register. The function of the two pins is as follows: DIR=0 DIR=1 ----- ----- p_ack Input Output p_ack_dir 0 1 BUSY_DSEL This bit is the bidirectional select for the p_bsy_ signal. When reset, p_bsy_ is fixed as an input. When set, p_bsy_ is a bidirectional signal. The p_bsy_dir_ pin will reflect the direction of p_bsy_. The switching of direction is controlled by the DIR bit of the Transfer Control Register. The function of the two pins is as follows: DIR=0 DIR=1 ----- ----- p_d_strb Output Input p_ds_dir_ 1 0 This bit also defines transfer protocol as follows: 1 = Data strobe is bidirectional. Master write transfer protocol is selected. 0 = Data strobe is fixed as an output. Master read/write transfer protocol is selected. DATA_SRC This bit specifies the data to be sourced during a memory clear operation. When set, the sourced data will be ones. When reset, the sourced data will be zeros. MEM_CLR This bit enables memory clear operation. Additionally, the DMA control registers need to be configured and DMA must be enabled. Parallel Port Interface Registers Parallel Data Register (P_DR) The Data Register is an 8-bit read/write port used to transfer data to an from the external device. In programmed I/O mode data written to this register is presented to the I/O pins if the DIR bit of the Transfer COntrol Register is 0. A read of this register will result in the data previously written or if the DIR bit of the Transfer Control Register is set to 1, the latched data from the last data strobe. The data port is not accessible via slave write cycles During DMA (P_DMA_ON=1). Any write cycles during DMA will not generate errors, the data will simply not be written. SInce both DMA and PIO share the same data register, internal loopback is possible by running a single byte DMA cycle followed by a PIO cycle to verify the data. This will test both the DMA and slave data paths. The reset state of this register is undefined. ADDR=14, Size=8 Bit ---------------------------------------------------------------------- | Addr | Bits | Description | Size | Type | ---------------------------------------------------------------------- | 14 | 7:0 | Parallel Data | 8 Bit| R/W | ---------------------------------------------------------------------- Transfer Control Register (P_TCR) The Transfer Control Register is an 8-bit register whose contents define/reflect the state of the external interface handshake and direction control signals. The DS, ACK, and BUSY-bits will reflect the state of the external pins, when read. Writing these bits defines a value to be driven onto the external pins if the individual direction select bits (DS_DSEL, ACK_DSEL, BUSY_DSEL) and the direction control bit (DIR) are configured such that these pins are outputs. The write bits and read bits are different. That means that values typically written to these bits may not be reflected on a read cycle. However, by setting the EN_DIAG bit of the Operation Control Register, these register bits become read/write (see the EN_DIAG bit description of the OCR). ADDR=15, Size=8 Bit ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 0 | DS | Data Strobe. | R/W | ---------------------------------------------------------------------- | 1 | ACK | Acknowledge. | R/W | ---------------------------------------------------------------------- | 2 | BUSY | Busy (active low). | R/W | ---------------------------------------------------------------------- | 3 | DIR | Direction Control. 0= Write to external | R/W | | | | Device. 1=Read. | | ---------------------------------------------------------------------- | 4 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- | 5 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- | 6 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- | 7 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- DS Reading this bit reflects the state of the bidirectional p_d_strb pin. Writing this bit with DS_DSEL=0 or with DS_SEL=1 and DIR=0 will cause the value written to be driven onto p_d_strb. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_d_strb. ACK Reading this bit reflects the state of the bidirectional p_ack pin. Writing this bit with ACK_DSEL=1 will cause the value written to be driven onto p_ack if DIR=1. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_ack. BUSY Reading this bit reflects the state of the bidirectional p_bsy_ pin. Writing this bit with BUSY_DSEL=1 will cause the value written to be driven onto p_bsy_ if DIR=1. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_bsy_. DIR This bit defines and controls the direction of data transfer: 0=write to external device, 1=read from external device. It is also driven externally on the p_d_dir_ pin. Note that this bit also controls the direction of DMA (except in the case of a memory clear operation, when the MEM_CLR bit defines DMA direction). The state of the DIR bit is reflected in the P_WRITE bit of the P_CSR. Reset state of this bit is 1. Output Register (P_OR) The Output Register is an 8-bit read/write register whose contents are driven onto the corresponding external pins. In diagnostic mode (EN_DIAG=1), bits 0-2 are gated onto Input Register bits 0-2. The external outputs remain low while diagnostic mode is enabled. All bits are 0 after reset. ADDR=16, Size=8 Bit ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 0 | SLCT_IN | Select in. This bit is output on the | R/W | | | | p_slct_in pin. | | ---------------------------------------------------------------------- | 1 | AFXN | Auto Feed. This bit is output on the | R/W | | | | p_afxn pin. | | ---------------------------------------------------------------------- | 2 | INIT | Initialize. This bit is output on the | R/W | | | | p_init pin. | | ---------------------------------------------------------------------- | 3 | --- | Reserved | R/W | ---------------------------------------------------------------------- | 4 | --- | Reserved | R/W | ---------------------------------------------------------------------- | 5 | --- | Reserved | R/W | ---------------------------------------------------------------------- | 6 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- | 7 | --- | Unused. Reads as 0. | RO | ---------------------------------------------------------------------- Input Register (P_IR) The Input Register is an 8-bit read/write register whose contents reflect the state of several external input pins and their corresponding interrupts. In diagnostic mode (EN_DIAG=1), bits 0-2 are driven from output register bits 0-2. ADDR=17, Size=8 Bit --------------------------------------------------------------------- | Bit | Mnemonic | Description | Type| --------------------------------------------------------------------- | 0 | ERR | Error input. This bit reflects the state | RO | | | | of the err input pin. | | --------------------------------------------------------------------- | 1 | SLCT | Select input. This bit reflects the state | RO | | | | of the slct input pin. | | --------------------------------------------------------------------- | 2 | PE | Paper empty. This bit reflects the state | RO | | | | of the p_pe_ input pin. | | --------------------------------------------------------------------- | 3 | --- | Unused. Reads as 0. | RO | --------------------------------------------------------------------- | 4 | --- | Unused. Reads as 0. | RO | --------------------------------------------------------------------- | 5 | --- | Unused. Reads as 0. | RO | --------------------------------------------------------------------- | 6 | --- | Unused. Reads as 0. | RO | --------------------------------------------------------------------- | 7 | --- | Unused. Reads as 0. | RO | --------------------------------------------------------------------- ERR, SLCT, PE These bits reflect the state of the corresponding input pins. Input Control Register This 16-bit read/write register is used to specify operation of the parallel port interrupts. Interrupt enables, polarity, and IRQ pending bits are contained in the register. The detailed function of these bits is described following the table. Reset value of this register is all bits 0. ADDR=18, Size=16 Bit ---------------------------------------------------------------------- | Bit | Mnemonic | Description | Type | ---------------------------------------------------------------------- | 0 | ERR_IRQ_EN | When set, enables ERR interrupts. | R/W | ---------------------------------------------------------------------- | 1 | ERR_IRP | ERR interrupt polarity. 1=on rising edge | R/W | | | | 0=on trailing edge. | | ---------------------------------------------------------------------- | 2 | SLCT_IRQ_EN| When set, enables SLCT interrupts. | R/W | ---------------------------------------------------------------------- | 3 | SLCT_IRP | SLCT interrupt polarity. 1=on rising edge| R/W | | | | 0=on trailing edge. | | ---------------------------------------------------------------------- | 4 | PE_IRQ_EN | When set, enables PE interrupts. | R/W | ---------------------------------------------------------------------- | 5 | PE_IRP | PE interrupt polarity. 1=on rising edge | R/W | | | | 0=on trailing edge. | | ---------------------------------------------------------------------- | 6 | BUSY_IRQ_EN| When set, enables BUSY interrupts. | R/W | ---------------------------------------------------------------------- | 7 | BUSY_IRP | BUSY interrupt polarity. 1=on rising edge| R/W | | | | 0=on trailing edge. | | ---------------------------------------------------------------------- | 8 | ACK_IRQ_EN | When set, enables ACK interrupts on | R/W | | | | rising edge of ack. | | ---------------------------------------------------------------------- | 9 | DS_IRQ_EN | When set, enables DS interrupts on the | R/W | | | | rising edge of ds. | | ---------------------------------------------------------------------- | 10 | ERR_IRQ | When set, error IRQ pending. | R/W | ---------------------------------------------------------------------- | 11 | SLCT_IRQ | When set, select IRQ pending. | R/W | ---------------------------------------------------------------------- | 12 | PE_IRQ | When set, select IRQ pending. | R/W | ---------------------------------------------------------------------- | 13 | BUSY_IRQ | When set, paper empty IRQ pending. | R/W | ---------------------------------------------------------------------- | 14 | ACK_IRQ | When set, acknowledge IRQ pending. | R/W | ---------------------------------------------------------------------- | 15 | DS_IRQ | When set, data strobe IRQ pending. | R/W | ---------------------------------------------------------------------- *_IRQ_EN When set, enables interrupts on the corresponding bits of the Input and Transfer Control registers. Note that the interrupt enable bit of the PD_SCR must also be enabled to allow a hardware interrupt to be generated. *_IRP Defines the polarity of the edge triggered interrupts on the corresponding bits of the Input Register. 0=Interrupt generated on the 1 to 0 transition of the signal. 1=Interrupt generated on the 0 to 1 transitions of the signal. Note that when configuring the interrupt polarity of a given signal, it ispossible to generate a false interrupt. It is suggested that when the interrupt polarities are being programmed, interrupts be disabled and all interrupt sources cleared upon completion of programming. ERR_IRQ, SLCT_IRQ, PE_IRQ, BUSY_IRQ When set, an interrupt is pending on the corresponding bit. The interrupt is cleared and the bit is reset when a one is written to the corresponding bit. Writing a 0 to those locations leaves thebit(s) unchanged. ACK_IRQ When set, an interrupt is pending due to the receipt of p_ack. The interrupt is set on the 0 to 1 transition of p_ack. This interrupt is intended to facilitate PIO transfers while configured as master under master write protocol. The interrupt is cleared and the bit is reset when a one is written to this bit. Writing a 0 to this location leaves the bit unchanged. DS_IRQ When set, an interrupt is pending due to the receipt of p_d_strb. This interrupt is intended to facilitate PIO transfers while configured as slave under master write protocol. The interrupt is cleared and the bit is reset when a one is written to this bit. Writing a 0 to this location leaves the bit unchanged. Parallel Port Programming Notes Parallel Port Interrupts The P_INT_PEND and P_ERR_PENDbits of the P_CSR reflect whether the PP has an interrupt source active or not. This will allow software to determine whether an interrupt is pending on the PP by performing one register read. If P_INT_PEND is set, then one or more of the following interrupt sources are active: Parallel Port Control/Status Register (P_CSR): - P_TC - Terminal Count Parallel Port Interrupt Control Register (P_ICR): - ERR_IRQ Error - SLCT_IRQ Select - PE_IRQ Paper Error - BUSY_IRQ Busy - ACK_IRQ Acknowledge - DS_IRQ Data Strobe If the P_ERR_PEND bit is set, the P_RESET must be toggles to reset the parallel port to recover from the error. Mode Selection When switching modes of operation of the parallel port, the P_DMA_ON bit should be 0 and the IDLE bit of the Transfer Control Register should be 1 before the mode is switched. This insures that no data transfer cycles are in progress. "Mode Selection" in this context means handshake specification, control signal direction selection, interface direction selection via the DIR bit of the Transferrr Control Register, and memory clear operations.