Begin3 Title: Verilog Behavioral Simulator (VBS) Version: 1.3.0 (alpha) Entered-date: June 29, 1996 Description: Simulator for Verilog HDL. Supports functions, tasks and module instantiation. Still lacks a lot of features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements. This version has some additional features. See the README file for more details. Keywords: Verilog, HDL, circuit, simulator Author: jching@aloha.com (Jimen Ching) Maintained-by: jching@aloha.com (Jimen Ching) Primary-site: sunsite.unc.edu /pub/Linux/apps/circuits 128kB vbs-1.3.0.tar.gz 1kB vbs-1.3.0.lsm Alternate-site: Not Yet Available Original-site: None Platform: C, C++, flex, bison Copying-policy: GPL End