From jcallen@Think.COM  Ukn Jul  6 13:49:27 1993
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From: Jerry Callen <jcallen@Think.COM>
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To: riscy@pyramid.com
In-Reply-To: Andrew Dyer's message of Thu, 1 Jul 93 22:39 PDT <m0oBdpx-00039LC@zarniwoop.uucp>
Subject: IDT7370
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Status: RO
X-Status: 

   Date: Thu, 1 Jul 93 22:39 PDT
   From: zarniwoop!adyer@world.std.com (Andrew Dyer)

   I still like the idea of using the LSI Logic family instead of the
   IDT.  For a project like this they have some advantages - mostly that
   the DRAM and bus sizing stuff is on-board.

I can't find the info I used to have on this chip family. I seem to recall
that the bus sizing stuff is very limited; basically, it lets you use a
narrow (8-bit) boot device, and that's it. But I could be wrong.

Are the FPU and non-FPU versions pin compatible?

   ...they all have a 4k/1k i/d cache and come in PGA packaging. (No lousy
   84PLCC sockets!)

Why is PGA a virtue and PLCC "lousy?" My one experience trying to remove a
high pin count PGA from a socket was not good, whereas I've pulled PLCCs
without hassle. PGA is more expensive to manufacture, too.

-- Jerry

 
From adyer@zarniwoop  Ukn Jul  2 21:43:56 1993
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Date: Thu, 1 Jul 93 22:39 PDT
From: adyer@zarniwoop (Andrew Dyer)
To: riscy@pyramid.com
Subject: IDT7370
Cc: caret@pyramid.com
Status: RO
X-Status: 

I still like the idea of using the LSI Logic family instead of the
IDT.  For a project like this they have some advantages - mostly that
the DRAM and bus sizing stuff is on-board.  They have three models
that I have info on - 33000 which is a MIPS 3000 core plus their
interface logic, 33020 which has the same mips core + glue logic +
plus a bit-blit engine and RAMDAC interface (for xterms on a chip),
and finally the 33050 which is a 33000 with MIPS FPU.  I believe they
all have a 4k/1k i/d cache and come in PGA packaging. (No lousy 84PLCC
sockets!)

As for I/O busses - the ISA bus IS a simple 8-bit bus.  I don't see
what all the whining is about.  VESA is kinda nasty and not well
defined.  If we are going to invest in a high speed bus, make it a
processor local bus, where some speed can be used not wasted
generating a bunch of other control signals.

As for FPGAs, I believe AMD gives away their PALASM s/w to program
MACH devices, I also have s/w for the Intel IFX780 and Xilinx which is
NOT free at work.  For a project like this FPGAs might have some
advantages - reconfiguration, one physical part to perform several
different tasks, real estate reduction, speed, and perhaps cost if the
s/w is not too expensive.

 
