From owner-riscy@pyramid.com  Thu Jul 15 21:02:36 1993
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Message-Id: <199307160101.AA24195@ophelia.cs.Colorado.EDU>
To: riscy@pyramid.com
Subject: MOM 3000 chipset
In-Reply-To: Your message of "Tue, 13 Jul 1993 16:27:29 PDT."
             <9307132327.AA07099@sword.eng.pyramid.com> 
Date: Thu, 15 Jul 1993 19:01:18 -0600
From: Drew Eckhardt <drew@ophelia.cs.Colorado.EDU>
Sender: owner-riscy@pyramid.com
Reply-To: riscy@pyramid.com


While this chip adresses many of our needs (ie, address/data DEMUX,
DRAM / VRAM control, video timing signal generation, AT keyboard
interface) but falls short in other areas.

Most notable is the chips abysmal DMA support :  

- There's no support for slave mode DMA.  This makes it impossible to 
	use the low cost NCR53c90 for synchronous SCSI, severely 
	limiting your bandwidth.  It also makes it impossible to 
	get slave mode DMA from IDE, etc. devices, meaning we'll 
	have to waste CPU cycles doing polled transfers when we
	recieve an appropraite interrupt.

- Support for bus mastering *is* there, Bus grant / requests could 
	be daisy chained to get something other than the AMC ILAC 
	on the bus.  However, if we use other busmastering devices
	(the NCR53c700 SCSI controller comes to mind immediately) we 
	increase the cost of the rest of the system,  not to mention
	hardware and software development time.  Also, the onboard
	support for busmasters wants to see a MUX'd address/data bus
	with signals like those from the ILAC / 3041/3051/3081.

Also, bus sizing is limited to 32 / 64 bits wide, and we want 
to use 8 and 16 bit peripherials. 

Obviously, we can design arround these limitations with external
hardware, but the cost of the necessary internal hardware must be 
considered when comparing the MOM chips with others like the 
3700.

 
