Subject: Re: R4xxx Cache size.

From: Andreas Busse <[email-masked]>
Date: Tue, 10 Aug 93 10:58:48 +0200

> >    The R4xxxx has a larger internal cache.
> >
> >R4000 : 8K I, 8K D
> >R4400 : 16K I, 16K D
> >
> >The maximum imposed by the R4000 architecture is 32K each for the primary
> >cache.  I don't know about the 4200 since I don't have a data book in front
> >of me like I do for the NEC Vr4000 and Vr4400, PC, SC, and MC variants :-)
>     
> Huh? Does that mean that the ARCHITECTURE defines a maximum CACHE size?
> According to current definitions here at the computer architecture group,
> cache size is an implementation aspect, and shouldn't be visible at the
> architectural level.
> 
> -----
> This means that the R4xxx has a bad design: the design mixes implementation 
> with architectural features. The R4000 isn't as clean as we thought. This
> means that we can't use the R4000 as the processor.... :-)
> -----

Oh, please stop that noise. I don't know who told you that the
cache size of a R4000 is limited to 32+32k. Can you tell me how it
would then be possible to add a secondary cache ????
The limitation, if there is one, is given by the chip size, not
by any architectural problem !
If you would take a look at the R4200 layout, you would see that
more than 70 percent of the chip space is used by rams !

Andy

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From: Drew Eckhardt <[email-masked]>
Date: Tue, 10 Aug 1993 03:39:21 -0600

Oh, please stop that noise. I don't know who told you that the
    cache size of a R4000 is limited to 32+32k. 

Like I said, what NEC is passing out as one of their data books. Generally,
these things are technically accurate, although I'm begining to have my 
doubts.

After reading a few more chapters of the data book including the 
one on caching, nothing beyond the number of virtual address bits 
used as a cache index in the author's examples seems to back this 
up.  In hindsight, the statement I summarized from the data book
doesn't really sanity check, in school you quickly learn that in
many (most?) classes you get reasonable grades by blindly reciting 
the text book contents and telling the instructors what they want
to hear :-(

    Can you tell me how it would then be possible to add a secondary cache ????

Again, I said *primary* cache size, which has nothing to do with 
the (presumably off chip) second level cache.

I'd take a look at the R4200 layout, but the local NEC distributor
didn't get anything on the 4000 series chips until Friday, and still
won't say anything about pricing or the 4200 :-(