Subject: R4000 chipsets

From: Andreas Busse <[email-masked]>
Date: Thu, 12 Aug 93 11:00:43 +0200

Hi Mipsers,

I called LSI Logic to get more informations about their chips
I've found in my Mips box.
Unfortunally, LSI Logic stopped R4000 support, but the support
guy was so kind to fax me some informations he found in the
Microprocessor Report 4/93.

Quoted:

ACER ANNOUNCES R4000 SYSTEM LOGIC CHIPS

Alternative Designs by MIPS, DeskStation Also in Development

[...]

Acer has announced a system-logic chip set for PC designers
using MIPS' R4000-family CPUs. The eight-chip set, called PICA,
is the first of several MIPS chips sets expected to be available
for the emerging Windows NT market. It provides a complete interface
to second-level cache, main memory, and I/O for an R4000PC or
R4400PC processor. It uses a new high-bandwith bus for video and
memory and connects standard PC buses for expandability. NEC will
probably second source for this chip set.
Two other forthcoming designs provide a "bridge" between the R4000
and standard 486 chip sets. DeskStation (Lenexa, Kansas) created
such a design for its ARCstation 1 system (see uPR 12/30/92, p. 4);
IDT has announced plans to market this implementation in 3Q93.
MIPS itself is developing a similar bridge that it expects Toshiba
and NEC to begin selling in 3Q93.

[...]

To reduce cost, PICA works with the "PC" version of the R4000, which
does not directly control a second-level cache. The CPU/Cache Controller
(CCC) provides the external cache support; this is cost-effective
because the R4000PC is much less expensive than the R4000SC which
includes a second-level cache controller.
The Acer design allows a second-level cache of either 128k or 256k.
(Minimal systems can omit this cache entirely.) A 128k cache typically
uses four 16kx16 parts, while the larger version requires 8 parts.

[...]

The PICA bus provides 200 MBytes per second of peak bandwith (burst mode)
to the memory and video subsystems. Three chips implement the interface
to main memory; the memory controller (MC) and two data buffers. The MC
provides address and control for up to 256 MB of DRAM.
[...]
The MC supports a memory data width of either 64 or 128 bits. With
relatively inexpensive 80-ns DRAMs, the memory can keep pace with the
25 MHz PICA bus; page mode hits return data in a 3-1-1-1 pattern.
>From the viewpoint of the 50MHz processor bus, this 32-byte read would
take 14 cycles.

[end of quoted material]

Here's the block diagram:

   +-------+       +----------+    +------+
   | R4000 |       | L2 cache |----|  L2  |
   |   PC  |       | 0...256k |    | Tags |
   +-------+       +----------+    +------+
       |                |             |
       +----------------|             |
            |           |             |
            |           |             |
        +-------+   +-----------+     |    
        | Data  |   |           |     |    +--------+  +---------+ 
        | FIFOs |   |   CCC     |-----+    | Data   |--| 8..256M |
        +-------+   |           |       +- | Buffers|  |  SIMMs  |
            |       +-----------+       |  + -------+  +---------+
            |             |             |                   |
            |             |             |  +--------+       |
 +-------+  |             | PICA bus    |  | Memory |       |
 | Video |---------------------------------| Ctrl.  |-------+
 | Card  |       |               |         +--------+
 +-------+       |               |
                 |               |
            +-----------+   +----------+
            |   DMA     |   |   I/O    |
            |   Ctrl.   |   |  Cache   |
            +-----------+   +----------+     +-----------+
 +--------+      |               |           |    ISA    |
 |        |----------------------------------|     or    |---- ISA/EISA Bus
 | local  |      |   Remote Bus  |           |    EISA   |
 |  I/O   |      |               |           | Interface |
 |        |      |               |           +-----------+
 +--------+  +----------+  +-------------+
             | Ethernet |  | Keyb./Mouse |
             +----------+  +-------------+

-------

That looks fine, at least for me.
Has someone a phone number of Acer ?

Cheers,
Andy

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              R&D Department            | Fax:    +49 (0)2636-80188
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---

From: Bill Broadley <[email-masked]>
Date: Thu, 12 Aug 1993 05:38:45 -0500 (EDT)

> It provides a complete interface to second-level cache, main memory, 
> and I/O for an R4000PC or R4400PC processor.

Sounds very good, getting the cheap cpu AND a 2nd level cache.

> and NEC to begin selling in 3Q93.

Two bridge chips sets due out nowish good.

> provides address and control for up to 256 MB of DRAM.

PICA?? Is this proprietary? How wide?  Clock speed?

256 MB sounds good, I'm this means 32 bit wide simms which is good.

> Has someone a phone number of Acer ?

    Acer Technologies Corp..... Tech Support .......... 408-922-0333

This sounds the best of all the choices, lets hope it's
affordable.

I see no limitation that would keep this system from being a 
formidable, well balanced, 486 killer system.

-- 
Bill					1st>	[email-masked]
[email-masked] <2nd 	3rd> 	             [email-masked]
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