Subject: Re: R4xxx Cache size, pedantic ramblings

From: [email-masked] (Rogier Wolff)
Date: Tue, 10 Aug 93 11:08:48 +0200

According to 

	_MIPS R4000 USER'S MANUAL_

	by Joseph Heinrich

	which happens to be what NEC is calling their 

	VR4000-SERIES(tm)ARCHITECTURE
			 ^^^^^^^^^^^^
	INCLUDING VR4400(tm)
	USER'S MANUAL

This agrees with "our" definition of architecture: architecture is
what the user will see of a processor. The cache size should be 
more or less transparent. A specialized timing program might figure
it out, the user manual might mention that the current chips have
a such-and-such cache size, but users shouldn't be able to poke
around at the cache such that they need to be aware of the cache
size. 

It seems that the R4xxxx designers found a reason
that requires the OS or the Users access to (part of) the cache,
and have limited an address field to 15 bits. This isn't really critical.

The '486 has : 

	1.  There is a single cache.
	2.  The i486 has an 8K cache.
	3.  The primary cache is set associative (I think  4-way).
	4.  Primary cache line size is 16 bytes
	5.  The primary cache is write-through.

Compare to R4000:
	1.  Primary I/D caches are separate.
This is an advantage: If one of the caches starts thrashing, the other
might still function properly. Thrashing is when a cache is completely
uneffective, because the program almost never references an element in
the cache.
	2.  The 4000PC has 8K I/D caches, the biggest R4000 series chips 
		SHIPPING have 16K I/D caches.
Ok. Larger caches are better.
	3.  The caches are direct mapped.
This is an disadvantage. Set associative is better (but the difference 
might on the average be neglectable).
Lets assume a cache size of 4000 bytes. Both caches can cache elements
at address 0, 1000, 2000 and 3000 at the same time. However should
a program reference 0, 4000, 8000 and 16000 at the same time, the set
associative cache will be able to cache them all four, whereas the 
direct mapped cache can only hold one of them.
	4.  Line size is user-configurable to either 16 or 32 bytes wide.
Depending on the speed of the page-mode, having a larger line size
will be worse or better.
	5.  The data cache can be write-back.
Depending on the application this is an advantage. Fact is that OS's
can do very little to optimize the use of this bit. You run a benchmark,
decide which setting of the bit is best, and leave it that way.
(Intel probably did this before releasing the chip..... :-)
	6.  All instructions are 32 bits.
This has nothing to do with caches.

				Roger.

---

From: Drew Eckhardt <[email-masked]>
Date: Tue, 10 Aug 1993 03:51:24 -0600

--------

    Compare to R4000:

Indirectly, it does.

I should have been more specific here : specifically, I was 
getting at the lack of variable sized instructions forcing the 
instructions to be bigger (ie, 32 bits for the R4000 vs. 8,16, etc. 
for the i486) meaning the R4000 will have larger code and will 
therefore require a larger cache to maintain the same hit-rate.

I should have generalized more and said 

"RISC chips have bigger code than CISC chips, and therefore will
need larger caches to have the same hit rate"

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